75720db391
The Xtensa architecture had been removed because it required special handling and depended on additional directories and files that became obsolete over time. This change is more aligned to other architectures. [Thomas: rebased on top of the "arch: improve definition of gcc mtune, mcpu, etc." patch]. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
224 lines
5.1 KiB
Plaintext
224 lines
5.1 KiB
Plaintext
config BR2_ARCH_IS_64
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bool
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choice
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prompt "Target Architecture"
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default BR2_i386
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help
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Select the target architecture family to build for.
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config BR2_arm
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bool "ARM (little endian)"
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Little endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_armeb
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bool "ARM (big endian)"
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Big endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_aarch64
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bool "AArch64"
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help
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Aarch64 is a 64-bit architecture developed by ARM Holdings.
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http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
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http://en.wikipedia.org/wiki/ARM
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config BR2_avr32
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bool "AVR32"
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select BR2_SOFT_FLOAT
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help
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The AVR32 is a 32-bit RISC microprocessor architecture designed by
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Atmel.
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http://www.atmel.com/
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http://en.wikipedia.org/wiki/Avr32
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config BR2_bfin
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bool "Blackfin"
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help
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The Blackfin is a family of 16 or 32-bit microprocessors developed,
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manufactured and marketed by Analog Devices.
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http://www.analog.com/
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http://en.wikipedia.org/wiki/Blackfin
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config BR2_i386
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bool "i386"
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help
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Intel i386 architecture compatible microprocessor
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http://en.wikipedia.org/wiki/I386
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config BR2_m68k
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bool "m68k"
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depends on BROKEN # ice in uclibc / inet_ntoa_r
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help
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Motorola 68000 family microprocessor
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http://en.wikipedia.org/wiki/M68k
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config BR2_microblazeel
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bool "Microblaze AXI (little endian)"
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
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based architecture (little endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_microblazebe
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bool "Microblaze non-AXI (big endian)"
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
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based architecture (non-AXI, big endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_mips
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bool "MIPS (big endian)"
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mipsel
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bool "MIPS (little endian)"
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64
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bool "MIPS64 (big endian)"
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select BR2_ARCH_IS_64
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64el
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bool "MIPS64 (little endian)"
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select BR2_ARCH_IS_64
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_powerpc
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bool "PowerPC"
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_sh
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bool "SuperH"
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help
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SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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config BR2_sh64
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bool "SuperH64"
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help
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SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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config BR2_sparc
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bool "SPARC"
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help
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SPARC (from Scalable Processor Architecture) is a RISC instruction
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set architecture (ISA) developed by Sun Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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config BR2_x86_64
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bool "x86_64"
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select BR2_ARCH_IS_64
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help
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x86-64 is an extension of the x86 instruction set (Intel i386
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architecture compatible microprocessor).
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http://en.wikipedia.org/wiki/X86_64
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config BR2_xtensa
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bool "Xtensa"
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help
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Xtensa is a Tensilica processor IP architecture.
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http://en.wikipedia.org/wiki/Xtensa
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http://www.tensilica.com/
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endchoice
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# The following string values are defined by the individual
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# Config.in.$ARCH files
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config BR2_ARCH
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string
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config BR2_ENDIAN
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string
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config BR2_GCC_TARGET_TUNE
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string
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config BR2_GCC_TARGET_ARCH
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string
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config BR2_GCC_TARGET_ABI
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string
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config BR2_GCC_TARGET_CPU
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string
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if BR2_arm || BR2_armeb
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source "arch/Config.in.arm"
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endif
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if BR2_aarch64
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source "arch/Config.in.aarch64"
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endif
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if BR2_avr32
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source "arch/Config.in.avr32"
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endif
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if BR2_bfin
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source "arch/Config.in.bfin"
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endif
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if BR2_m68k
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source "arch/Config.in.m68k"
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endif
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if BR2_microblazeel || BR2_microblazebe
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source "arch/Config.in.microblaze"
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endif
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if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
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source "arch/Config.in.mips"
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endif
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if BR2_powerpc
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source "arch/Config.in.powerpc"
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endif
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if BR2_sh || BR2_sh64
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source "arch/Config.in.sh"
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endif
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if BR2_sparc
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source "arch/Config.in.sparc"
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endif
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if BR2_i386 || BR2_x86_64
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source "arch/Config.in.x86"
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endif
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if BR2_xtensa
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source "arch/Config.in.xtensa"
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endif
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