f9ea52db9a
ref #1083
102 lines
2.3 KiB
C++
102 lines
2.3 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and Panda A2
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <platform.h>
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#include <board.h>
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#include <processor_driver.h>
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#include <pic.h>
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#include <kernel/irq.h>
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using namespace Genode;
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namespace Kernel { void init_platform(); }
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/**
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* Interrupts that core shall provide to users
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*/
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static unsigned irq_ids[] =
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{
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Board::GP_TIMER_3_IRQ,
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Board::TL16C750_1_IRQ,
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Board::TL16C750_2_IRQ,
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Board::TL16C750_4_IRQ,
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Board::GPIO1_IRQ,
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Board::GPIO2_IRQ,
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Board::GPIO3_IRQ,
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Board::GPIO4_IRQ,
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Board::GPIO5_IRQ,
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Board::GPIO6_IRQ,
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Board::HSUSB_EHCI_IRQ
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};
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enum { IRQ_IDS_SIZE = sizeof(irq_ids)/sizeof(irq_ids[0]) };
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void Kernel::init_platform()
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{
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/* make user IRQs become known by cores IRQ session backend and kernel */
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static uint8_t _irqs[IRQ_IDS_SIZE][sizeof(Irq)];
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for (unsigned i = 0; i < IRQ_IDS_SIZE; i++) {
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new (_irqs[i]) Irq(irq_ids[i]);
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}
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}
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unsigned * Platform::_irq(unsigned const i)
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{
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return i < IRQ_IDS_SIZE ? &irq_ids[i] : 0;
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}
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
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{ Board::DSS_MMIO_BASE, Board::DSS_MMIO_SIZE },
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{ Board::DISPC_MMIO_BASE, Board::DISPC_MMIO_SIZE },
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{ Board::HDMI_MMIO_BASE, Board::HDMI_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* core timer and PIC */
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{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
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Board::CORTEX_A9_PRIVATE_MEM_SIZE },
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/* core UART */
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{ Board::TL16C750_3_MMIO_BASE, Board::TL16C750_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Cpu::User_context::User_context() { cpsr = Psr::init_user(); }
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