176 lines
4.1 KiB
C++
176 lines
4.1 KiB
C++
/*
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* \brief CPU driver for core
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* \author Norman Feske
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* \author Martin stein
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* \date 2012-08-30
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CPU__ARM_V6_H_
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#define _CPU__ARM_V6_H_
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/* Genode includes */
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#include <board/imx31.h>
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#include <base/printf.h>
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/* core includes */
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#include <cpu/arm.h>
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namespace Arm_v6
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{
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using namespace Genode;
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/**
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* CPU driver for core
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*/
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struct Cpu : Arm::Cpu
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{
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/**
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* Cache type register
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*/
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struct Ctr : Arm::Cpu::Ctr
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{
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struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
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};
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/**
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* System control register
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*/
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struct Sctlr : Arm::Cpu::Sctlr
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{
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struct W : Bitfield<3,1> { }; /* enable write buffer */
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struct Unused_0 : Bitfield<4,3> { }; /* shall be ones */
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struct B : Bitfield<7,1> /* Memory system endianess */
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{
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enum { LITTLE = 0 };
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};
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struct S : Bitfield<8,1> { }; /* enbale MMU protection */
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struct R : Bitfield<9,1> { }; /* enbale ROM protection */
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struct L4 : Bitfield<15,1> { }; /* raise T bit on LOAD-to-PC */
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struct Dt : Bitfield<16,1> { }; /* global data TCM enable */
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struct It : Bitfield<18,1> { }; /* global instruction TCM enable */
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struct U : Bitfield<22,1> { }; /* enable unaligned data access */
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struct Xp : Bitfield<23,1> { }; /* disable subpage AP bits */
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struct Unused_1 : Bitfield<26,6> { }; /* shall not be modified */
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/**
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* Get static base value for writes
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*/
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static access_t base_value() {
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return Unused_0::reg_mask() | Unused_1::masked(read()); }
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/**
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* Value for the switch to virtual mode in kernel
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*/
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static access_t init_virt_kernel()
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{
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return base_value() |
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Arm::Cpu::Sctlr::init_virt_kernel() |
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W::bits(0) |
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B::bits(B::LITTLE) |
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S::bits(0) |
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R::bits(0) |
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L4::bits(0) |
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Dt::bits(0) |
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It::bits(0) |
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U::bits(0) |
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Xp::bits(1);
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}
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/**
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* Value for the initial kernel entry
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*/
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static access_t init_phys_kernel()
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{
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return base_value() |
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Arm::Cpu::Sctlr::init_phys_kernel() |
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W::bits(0) |
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B::bits(B::LITTLE) |
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S::bits(0) |
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R::bits(0) |
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L4::bits(0) |
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Dt::bits(1) |
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It::bits(1) |
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U::bits(0) |
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Xp::bits(1);
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}
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};
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/**
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* Translation table base control register 0
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*/
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struct Ttbr0 : Arm::Cpu::Ttbr0
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{
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struct P : Bitfield<2,1> { }; /* memory controller ECC enabled */
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/**
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* Value for the switch to virtual mode in kernel
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*
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* \param section_table initial section table
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*/
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static access_t init_virt_kernel(addr_t const sect_table)
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{
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return Arm::Cpu::Ttbr0::init_virt_kernel(sect_table) |
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P::bits(0);
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}
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};
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/**
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* If page descriptor bits [13:12] are restricted
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*/
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static bool restricted_page_mappings() {
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return Ctr::P::get(Ctr::read()); }
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/**
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* Configure this module appropriately for the first kernel run
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*/
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static void init_phys_kernel()
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{
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Board::prepare_kernel();
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Sctlr::write(Sctlr::init_phys_kernel());
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flush_tlb();
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/* check for mapping restrictions */
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if (restricted_page_mappings()) {
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PDBG("Insufficient driver for page tables");
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while (1) ;
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}
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}
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/**
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* Switch to the virtual mode in kernel
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*
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* \param section_table section translation table of the initial
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* address space this function switches to
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* \param process_id process ID of the initial address space
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*/
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static void init_virt_kernel(addr_t const section_table,
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unsigned long const process_id)
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{
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Cidr::write(process_id);
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Dacr::write(Dacr::init_virt_kernel());
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Ttbr0::write(Ttbr0::init_virt_kernel(section_table));
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Ttbcr::write(Ttbcr::init_virt_kernel());
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Sctlr::write(Sctlr::init_virt_kernel());
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}
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};
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}
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void Arm::Cpu::flush_data_caches() {
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asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }
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#endif /* _CPU__ARM_V6_H_ */
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