5c7436bf10
Whether an SoC has the multiprocessing extensions can be read out from the identification registers, and does not need to be specified in each board header. Ref #3445
140 lines
3.2 KiB
C++
140 lines
3.2 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2012-09-11
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__ARM__CPU_SUPPORT_H_
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#define _CORE__SPEC__ARM__CPU_SUPPORT_H_
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/* Genode includes */
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#include <util/register.h>
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#include <cpu/cpu_state.h>
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#include <base/internal/align_at.h>
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#include <hw/spec/arm/cpu.h>
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/* local includes */
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#include <kernel/interface_support.h>
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#include <kernel/kernel.h>
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#include <board.h>
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#include <util.h>
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namespace Kernel { struct Thread_fault; }
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namespace Genode {
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using sizet_arithm_t = Genode::uint64_t;
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struct Arm_cpu;
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}
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struct Genode::Arm_cpu : public Hw::Arm_cpu
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{
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struct Fpu_context
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{
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uint32_t fpscr { 1UL << 24 }; /* VFP/SIMD - status/control register */
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uint64_t d0_d31[32]; /* VFP/SIMD - general purpose registers */
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};
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struct alignas(4) Context : Cpu_state, Fpu_context
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{
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Context(bool privileged);
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};
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/**
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* This class comprises ARM specific protection domain attributes
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*/
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struct Mmu_context
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{
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Cidr::access_t cidr;
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Ttbr0::access_t ttbr0;
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Mmu_context(addr_t page_table_base);
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~Mmu_context();
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uint8_t id() { return cidr; }
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};
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/**
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* Invalidate all entries of all instruction caches
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*/
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static void invalidate_instr_cache() {
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" :: "r" (0) : ); }
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/**
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* Invalidate all branch predictions
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*/
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static void invalidate_branch_predicts() {
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asm volatile ("mcr p15, 0, r0, c7, c5, 6" ::: "r0"); };
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static constexpr addr_t line_size = 1 << Board::CACHE_LINE_SIZE_LOG2;
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static constexpr addr_t line_align_mask = ~(line_size - 1);
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/**
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* Clean and invalidate data-cache for virtual region
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* 'base' - 'base + size'
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*/
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static void clean_invalidate_data_cache_by_virt_region(addr_t base,
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size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Dccimvac::write(base); }
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}
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/**
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* Invalidate instruction-cache for virtual region
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* 'base' - 'base + size'
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*/
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void invalidate_instr_cache_by_virt_region(addr_t base,
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size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Icimvau::write(base); }
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}
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/**
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* Invalidate TLB regarding the given address space id
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*/
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static void invalidate_tlb(unsigned asid)
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{
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if (asid) Tlbiasid::write(asid);
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else Tlbiall::write(0);
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}
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void switch_to(Context&, Mmu_context & o)
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{
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if (o.cidr == 0) return;
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Cidr::access_t cidr = Cidr::read();
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if (cidr != o.cidr) {
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Cidr::write(o.cidr);
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Ttbr0::write(o.ttbr0);
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}
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}
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static void mmu_fault(Context & c, Kernel::Thread_fault & fault);
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static void mmu_fault_status(Fsr::access_t fsr,
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Kernel::Thread_fault & fault);
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/*************
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** Dummies **
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*************/
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return 0; }
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};
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#endif /* _CORE__SPEC__ARM__CPU_SUPPORT_H_ */
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