73eb7a8d4b
Instead of mapping all physical memory 1:1 into core/kernel's address space, this commit limits the 1:1 mapping to the binary image, and I/O memory regions used by the kernel only. All subsequent memory accesses of core are done by mapping the corresponding memory on demand, and not necessarily 1:1. This commit has several side effects: The page table code had to be revisited completely. The kernel inserts no longer anything into the page tables, apart from the initial translations to have the core/kernel image available when enabling the MMU. The page tables and higher level translation tables are no longer named Tlb, but Translation_table instead. There is no indirection class required to define the translation tables of a concrete SoC, the appropriated ARM specifier is sufficient. The ability to map core's memory the same way like it's done for all other protection domains, makes a special treatment of core's threads (no context area) obsolete. Ref #567 (partly solves it) Fix #723 Fix #1068
57 lines
1.3 KiB
C++
57 lines
1.3 KiB
C++
/*
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* \brief Parts of platform that are specific to Arndale
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <board.h>
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#include <platform.h>
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#include <pic.h>
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#include <processor_driver.h>
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#include <timer.h>
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using namespace Genode;
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::GIC_CPU_MMIO_BASE, Board::GIC_CPU_MMIO_SIZE },
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{ Board::MCT_MMIO_BASE, Board::MCT_MMIO_SIZE },
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{ Board::UART_2_MMIO_BASE, 0x1000 },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); }
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