699 lines
19 KiB
C++
699 lines
19 KiB
C++
/*
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* \brief x86_64 page table definitions
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* \author Adrian-Ken Rueegsegger
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__X86_64__PAGE_TABLE_H_
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#define _SRC__LIB__HW__SPEC__X86_64__PAGE_TABLE_H_
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#include <hw/assert.h>
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#include <hw/page_flags.h>
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#include <hw/page_table_allocator.h>
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#include <hw/util.h>
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#include <util/misc_math.h>
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#include <util/register.h>
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namespace Hw
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{
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/**
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* IA-32e paging translates 48-bit linear addresses to 52-bit physical
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* addresses. Translation structures are hierarchical and four levels
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* deep.
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*
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* For detailed information refer to Intel SDM Vol. 3A, section 4.5.
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*/
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enum {
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SIZE_LOG2_4KB = 12,
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SIZE_LOG2_2MB = 21,
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SIZE_LOG2_1GB = 30,
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SIZE_LOG2_512GB = 39,
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SIZE_LOG2_256TB = 48,
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};
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class Level_4_translation_table;
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class Pml4_table;
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class Page_table;
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/**
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* IA-32e page directory template.
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*
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* Page directories can refer to paging structures of the next higher level
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* or directly map page frames by using large page mappings.
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*
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* \param PAGE_SIZE_LOG2 virtual address range size in log2
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* of a single table entry
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* \param SIZE_LOG2 virtual address range size in log2 of whole table
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*/
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template <typename ENTRY, unsigned PAGE_SIZE_LOG2, unsigned SIZE_LOG2>
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class Page_directory;
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/**
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* IA-32e common descriptor.
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*
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* Table entry containing descriptor fields common to all four levels.
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*/
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struct Common_descriptor : Genode::Register<64>
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{
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struct P : Bitfield<0, 1> { }; /* present */
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struct Rw : Bitfield<1, 1> { }; /* read/write */
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struct Us : Bitfield<2, 1> { }; /* user/supervisor */
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struct Pwt : Bitfield<3, 1> { }; /* write-through */
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struct Pcd : Bitfield<4, 1> { }; /* cache disable */
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struct A : Bitfield<5, 1> { }; /* accessed */
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struct D : Bitfield<6, 1> { }; /* dirty */
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struct Xd : Bitfield<63, 1> { }; /* execute-disable */
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static bool present(access_t const v) { return P::get(v); }
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static access_t create(Page_flags const &flags)
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{
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return P::bits(1)
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| Rw::bits(flags.writeable)
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| Us::bits(!flags.privileged)
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| Xd::bits(!flags.executable);
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}
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/**
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* Return descriptor value with cleared accessed and dirty flags. These
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* flags can be set by the MMU.
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*/
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static access_t clear_mmu_flags(access_t value)
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{
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A::clear(value);
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D::clear(value);
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return value;
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}
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};
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}
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class Hw::Level_4_translation_table
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{
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private:
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static constexpr size_t PAGE_SIZE_LOG2 = SIZE_LOG2_4KB;
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static constexpr size_t SIZE_LOG2 = SIZE_LOG2_2MB;
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static constexpr size_t MAX_ENTRIES = 1UL << (SIZE_LOG2-PAGE_SIZE_LOG2);
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static constexpr size_t PAGE_SIZE = 1UL << PAGE_SIZE_LOG2;
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static constexpr size_t PAGE_MASK = ~((1UL << PAGE_SIZE_LOG2) - 1);
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class Misaligned {};
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class Invalid_range {};
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class Double_insertion {};
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struct Descriptor : Common_descriptor
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{
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using Common = Common_descriptor;
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struct Pat : Bitfield<7, 1> { }; /* page attribute table */
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struct G : Bitfield<8, 1> { }; /* global */
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struct Pa : Bitfield<12, 36> { }; /* physical address */
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struct Mt : Genode::Bitset_3<Pwt, Pcd, Pat> { }; /* memory type */
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static access_t create(Page_flags const &flags, addr_t const pa)
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{
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/* XXX: Set memory type depending on active PAT */
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return Common::create(flags)
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| G::bits(flags.global)
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| Pa::masked(pa);
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}
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};
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typename Descriptor::access_t _entries[MAX_ENTRIES];
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struct Insert_func
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{
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Page_flags const & flags;
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Insert_func(Page_flags const & flags)
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: flags(flags) { }
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void operator () (addr_t const vo, addr_t const pa,
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size_t const size,
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Descriptor::access_t &desc)
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{
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if ((vo & ~PAGE_MASK) || (pa & ~PAGE_MASK) ||
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size < PAGE_SIZE)
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{
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throw Invalid_range();
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}
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Descriptor::access_t table_entry =
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Descriptor::create(flags, pa);
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if (Descriptor::present(desc) &&
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Descriptor::clear_mmu_flags(desc) != table_entry)
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{
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throw Double_insertion();
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}
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desc = table_entry;
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}
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};
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struct Remove_func
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{
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void operator () (addr_t /* vo */, addr_t /* pa */, size_t /* size */,
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Descriptor::access_t &desc)
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{ desc = 0; }
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};
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template <typename FUNC>
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void _range_op(addr_t vo, addr_t pa, size_t size, FUNC &&func)
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{
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for (size_t i = vo >> PAGE_SIZE_LOG2; size > 0;
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i = vo >> PAGE_SIZE_LOG2) {
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assert (i < MAX_ENTRIES);
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addr_t end = (vo + PAGE_SIZE) & PAGE_MASK;
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size_t sz = Genode::min(size, end-vo);
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func(vo, pa, sz, _entries[i]);
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/* check whether we wrap */
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if (end < vo) return;
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size = size - sz;
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vo += sz;
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pa += sz;
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}
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}
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public:
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using Allocator = Page_table_allocator<1UL << SIZE_LOG2_4KB>;
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static constexpr size_t MIN_PAGE_SIZE_LOG2 = SIZE_LOG2_4KB;
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static constexpr size_t ALIGNM_LOG2 = SIZE_LOG2_4KB;
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/**
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* IA-32e page table (Level 4)
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*
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* A page table consists of 512 entries that each maps a 4KB page
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* frame. For further details refer to Intel SDM Vol. 3A, table 4-19.
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*/
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Level_4_translation_table()
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{
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if (!aligned(this, ALIGNM_LOG2)) throw Misaligned();
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Genode::memset(&_entries, 0, sizeof(_entries));
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}
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/**
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* Returns True if table does not contain any page mappings.
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*/
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bool empty()
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{
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for (unsigned i = 0; i < MAX_ENTRIES; i++)
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if (Descriptor::present(_entries[i]))
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return false;
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return true;
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}
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/**
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* Insert translations into this table
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*
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* \param vo offset of the virtual region represented
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* by the translation within the virtual
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* region represented by this table
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* \param pa base of the physical backing store
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* \param size size of the translated region
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* \param flags mapping flags
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* \param alloc second level translation table allocator
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*/
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void insert_translation(addr_t vo, addr_t pa, size_t size,
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Page_flags const & flags, Allocator &)
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{
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this->_range_op(vo, pa, size, Insert_func(flags));
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}
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/**
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* Remove translations that overlap with a given virtual region
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*
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* \param vo region offset within the tables virtual region
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* \param size region size
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* \param alloc second level translation table allocator
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*/
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void remove_translation(addr_t vo, size_t size, Allocator &)
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{
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this->_range_op(vo, 0, size, Remove_func());
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}
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} __attribute__((aligned(1 << ALIGNM_LOG2)));
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template <typename ENTRY, unsigned PAGE_SIZE_LOG2, unsigned SIZE_LOG2>
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class Hw::Page_directory
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{
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private:
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static constexpr size_t MAX_ENTRIES = 1UL << (SIZE_LOG2-PAGE_SIZE_LOG2);
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static constexpr size_t PAGE_SIZE = 1UL << PAGE_SIZE_LOG2;
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static constexpr size_t PAGE_MASK = ~((1UL << PAGE_SIZE_LOG2) - 1);
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using Allocator = Page_table_allocator<1UL << SIZE_LOG2_4KB>;
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class Misaligned {};
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class Invalid_range {};
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class Double_insertion {};
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struct Base_descriptor : Common_descriptor
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{
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using Common = Common_descriptor;
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struct Ps : Common::template Bitfield<7, 1> { }; /* page size */
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static bool maps_page(access_t const v) { return Ps::get(v); }
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};
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struct Page_descriptor : Base_descriptor
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{
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using Base = Base_descriptor;
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/**
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* Global attribute
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*/
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struct G : Base::template Bitfield<8, 1> { };
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/**
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* Page attribute table
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*/
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struct Pat : Base::template Bitfield<12, 1> { };
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/**
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* Physical address
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*/
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struct Pa : Base::template Bitfield<PAGE_SIZE_LOG2,
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48 - PAGE_SIZE_LOG2> { };
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/**
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* Memory type
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*/
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struct Mt : Base::template Bitset_3<Base::Pwt,
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Base::Pcd, Pat> { };
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static typename Base::access_t create(Page_flags const &flags,
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addr_t const pa)
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{
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/* XXX: Set memory type depending on active PAT */
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return Base::create(flags)
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| Base::Ps::bits(1)
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| G::bits(flags.global)
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| Pa::masked(pa);
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}
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};
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struct Table_descriptor : Base_descriptor
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{
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using Base = Base_descriptor;
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/**
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* Physical address
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*/
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struct Pa : Base::template Bitfield<12, 36> { };
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/**
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* Memory types
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*/
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struct Mt : Base::template Bitset_2<Base::Pwt,
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Base::Pcd> { };
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static typename Base::access_t create(addr_t const pa)
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{
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/* XXX: Set memory type depending on active PAT */
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static Page_flags flags { RW, EXEC, USER, NO_GLOBAL,
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RAM, Genode::CACHED };
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return Base::create(flags) | Pa::masked(pa);
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}
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};
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typename Base_descriptor::access_t _entries[MAX_ENTRIES];
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struct Insert_func
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{
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using Descriptor = Base_descriptor;
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Page_flags const & flags;
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Allocator & alloc;
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Insert_func(Page_flags const & flags,
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Allocator & alloc)
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: flags(flags), alloc(alloc) { }
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void operator () (addr_t const vo, addr_t const pa,
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size_t const size,
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typename Descriptor::access_t &desc)
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{
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using Td = Table_descriptor;
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using access_t = typename Descriptor::access_t;
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/* can we insert a large page mapping? */
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if (!((vo & ~PAGE_MASK) || (pa & ~PAGE_MASK) ||
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size < PAGE_SIZE))
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{
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access_t table_entry = Page_descriptor::create(flags, pa);
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if (Descriptor::present(desc) &&
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Descriptor::clear_mmu_flags(desc) != table_entry) {
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throw Double_insertion(); }
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desc = table_entry;
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return;
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}
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/* we need to use a next level table */
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if (!Descriptor::present(desc)) {
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/* create and link next level table */
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ENTRY & table = alloc.construct<ENTRY>();
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desc = (access_t) Td::create(alloc.phys_addr(table));
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} else if (Descriptor::maps_page(desc)) {
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throw Double_insertion();
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}
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/* insert translation */
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ENTRY & table = alloc.virt_addr<ENTRY>(Td::Pa::masked(desc));
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table.insert_translation(vo - (vo & PAGE_MASK), pa, size,
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flags, alloc);
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}
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};
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struct Remove_func
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{
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Allocator & alloc;
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Remove_func(Allocator & alloc) : alloc(alloc) { }
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void operator () (addr_t const vo, addr_t /* pa */,
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size_t const size,
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typename Base_descriptor::access_t &desc)
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{
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if (Base_descriptor::present(desc)) {
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if (Base_descriptor::maps_page(desc)) {
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desc = 0;
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} else {
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using Td = Table_descriptor;
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/* use allocator to retrieve virt address of table */
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ENTRY & table = alloc.virt_addr<ENTRY>(Td::Pa::masked(desc));
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addr_t const table_vo = vo - (vo & PAGE_MASK);
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table.remove_translation(table_vo, size, alloc);
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if (table.empty()) {
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alloc.destruct<ENTRY>(table);
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desc = 0;
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}
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}
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}
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}
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};
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template <typename FUNC>
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void _range_op(addr_t vo, addr_t pa, size_t size, FUNC &&func)
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{
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for (size_t i = vo >> PAGE_SIZE_LOG2; size > 0;
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i = vo >> PAGE_SIZE_LOG2)
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{
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assert (i < MAX_ENTRIES);
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addr_t end = (vo + PAGE_SIZE) & PAGE_MASK;
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size_t sz = Genode::min(size, end-vo);
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func(vo, pa, sz, _entries[i]);
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/* check whether we wrap */
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if (end < vo) return;
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size = size - sz;
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vo += sz;
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pa += sz;
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}
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}
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public:
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static constexpr size_t MIN_PAGE_SIZE_LOG2 = SIZE_LOG2_4KB;
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static constexpr size_t ALIGNM_LOG2 = SIZE_LOG2_4KB;
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Page_directory()
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{
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if (!aligned(this, ALIGNM_LOG2)) throw Misaligned();
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Genode::memset(&_entries, 0, sizeof(_entries));
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}
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/**
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* Returns True if table does not contain any page mappings.
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*
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* \return false if an entry is present, True otherwise
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*/
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bool empty()
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{
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for (unsigned i = 0; i < MAX_ENTRIES; i++)
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if (Base_descriptor::present(_entries[i]))
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return false;
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return true;
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}
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/**
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* Insert translations into this table
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*
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* \param vo offset of the virtual region represented
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* by the translation within the virtual
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* region represented by this table
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* \param pa base of the physical backing store
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* \param size size of the translated region
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* \param flags mapping flags
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* \param alloc second level translation table allocator
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*/
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void insert_translation(addr_t vo, addr_t pa, size_t size,
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Page_flags const & flags,
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Allocator & alloc) {
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_range_op(vo, pa, size, Insert_func(flags, alloc)); }
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/**
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* Remove translations that overlap with a given virtual region
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*
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* \param vo region offset within the tables virtual region
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* \param size region size
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* \param alloc second level translation table allocator
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*/
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void remove_translation(addr_t vo, size_t size, Allocator & alloc) {
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_range_op(vo, 0, size, Remove_func(alloc)); }
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};
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namespace Hw {
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struct Level_3_translation_table :
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Page_directory<
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Level_4_translation_table,
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SIZE_LOG2_2MB, SIZE_LOG2_1GB>
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{ } __attribute__((aligned(1 << ALIGNM_LOG2)));
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struct Level_2_translation_table :
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Page_directory<
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Level_3_translation_table,
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SIZE_LOG2_1GB, SIZE_LOG2_512GB>
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{ } __attribute__((aligned(1 << ALIGNM_LOG2)));
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}
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class Hw::Pml4_table
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{
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public:
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using Allocator = Page_table_allocator<1UL << SIZE_LOG2_4KB>;
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private:
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static constexpr size_t PAGE_SIZE_LOG2 = SIZE_LOG2_512GB;
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static constexpr size_t SIZE_LOG2 = SIZE_LOG2_256TB;
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static constexpr size_t SIZE_MASK = (1UL << SIZE_LOG2) - 1;
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static constexpr size_t MAX_ENTRIES = 512;
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static constexpr size_t PAGE_SIZE = 1UL << PAGE_SIZE_LOG2;
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static constexpr size_t PAGE_MASK = ~((1UL << PAGE_SIZE_LOG2) - 1);
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class Misaligned {};
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class Invalid_range {};
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struct Descriptor : Common_descriptor
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{
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struct Pa : Bitfield<12, SIZE_LOG2> { }; /* physical address */
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struct Mt : Genode::Bitset_2<Pwt, Pcd> { }; /* memory type */
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static access_t create(addr_t const pa)
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{
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/* XXX: Set memory type depending on active PAT */
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static Page_flags flags { RW, EXEC, USER, NO_GLOBAL,
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RAM, Genode::CACHED };
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return Common_descriptor::create(flags) | Pa::masked(pa);
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}
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};
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typename Descriptor::access_t _entries[MAX_ENTRIES];
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using ENTRY = Level_2_translation_table;
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struct Insert_func
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{
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Page_flags const & flags;
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Allocator & alloc;
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Insert_func(Page_flags const & flags,
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Allocator & alloc)
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: flags(flags), alloc(alloc) { }
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void operator () (addr_t const vo, addr_t const pa,
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size_t const size,
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Descriptor::access_t &desc)
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{
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/* we need to use a next level table */
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if (!Descriptor::present(desc)) {
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/* create and link next level table */
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ENTRY & table = alloc.construct<ENTRY>();
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desc = Descriptor::create(alloc.phys_addr(table));
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}
|
|
|
|
/* insert translation */
|
|
ENTRY & table = alloc.virt_addr<ENTRY>(Descriptor::Pa::masked(desc));
|
|
addr_t const table_vo = vo - (vo & PAGE_MASK);
|
|
table.insert_translation(table_vo, pa, size, flags, alloc);
|
|
}
|
|
};
|
|
|
|
struct Remove_func
|
|
{
|
|
Allocator & alloc;
|
|
|
|
Remove_func(Allocator & alloc) : alloc(alloc) { }
|
|
|
|
void operator () (addr_t const vo, addr_t /* pa */,
|
|
size_t const size,
|
|
Descriptor::access_t &desc)
|
|
{
|
|
if (Descriptor::present(desc)) {
|
|
/* use allocator to retrieve virt address of table */
|
|
ENTRY & table = alloc.virt_addr<ENTRY>(Descriptor::Pa::masked(desc));
|
|
addr_t const table_vo = vo - (vo & PAGE_MASK);
|
|
table.remove_translation(table_vo, size, alloc);
|
|
if (table.empty()) {
|
|
alloc.destruct<ENTRY>(table);
|
|
desc = 0;
|
|
}
|
|
}
|
|
}
|
|
};
|
|
|
|
template <typename FUNC>
|
|
void _range_op(addr_t vo, addr_t pa, size_t size, FUNC &&func)
|
|
{
|
|
for (size_t i = (vo & SIZE_MASK) >> PAGE_SIZE_LOG2; size > 0;
|
|
i = (vo & SIZE_MASK) >> PAGE_SIZE_LOG2) {
|
|
assert (i < MAX_ENTRIES);
|
|
addr_t end = (vo + PAGE_SIZE) & PAGE_MASK;
|
|
size_t sz = Genode::min(size, end-vo);
|
|
|
|
func(vo, pa, sz, _entries[i]);
|
|
|
|
/* check whether we wrap */
|
|
if (end < vo) return;
|
|
|
|
size = size - sz;
|
|
vo += sz;
|
|
pa += sz;
|
|
}
|
|
}
|
|
|
|
protected:
|
|
|
|
/**
|
|
* Return how many entries of an alignment fit into region
|
|
*/
|
|
static constexpr size_t _count(size_t region, size_t alignment)
|
|
{
|
|
return Genode::align_addr<size_t>(region, alignment)
|
|
/ (1UL << alignment);
|
|
}
|
|
|
|
public:
|
|
|
|
static constexpr size_t MIN_PAGE_SIZE_LOG2 = SIZE_LOG2_4KB;
|
|
static constexpr size_t ALIGNM_LOG2 = SIZE_LOG2_4KB;
|
|
|
|
Pml4_table()
|
|
{
|
|
if (!aligned(this, ALIGNM_LOG2)) throw Misaligned();
|
|
Genode::memset(&_entries, 0, sizeof(_entries));
|
|
}
|
|
|
|
explicit Pml4_table(Pml4_table & kernel_table) : Pml4_table()
|
|
{
|
|
static size_t first = (0xffffffc000000000 & SIZE_MASK) >> PAGE_SIZE_LOG2;
|
|
for (size_t i = first; i < MAX_ENTRIES; i++)
|
|
_entries[i] = kernel_table._entries[i];
|
|
}
|
|
|
|
/**
|
|
* Returns True if table does not contain any page mappings.
|
|
*
|
|
* \return false if an entry is present, True otherwise
|
|
*/
|
|
bool empty()
|
|
{
|
|
for (unsigned i = 0; i < MAX_ENTRIES; i++)
|
|
if (Descriptor::present(_entries[i]))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* Insert translations into this table
|
|
*
|
|
* \param vo offset of the virtual region represented
|
|
* by the translation within the virtual
|
|
* region represented by this table
|
|
* \param pa base of the physical backing store
|
|
* \param size size of the translated region
|
|
* \param flags mapping flags
|
|
* \param alloc second level translation table allocator
|
|
*/
|
|
void insert_translation(addr_t vo, addr_t pa, size_t size,
|
|
Page_flags const & flags, Allocator & alloc) {
|
|
_range_op(vo, pa, size, Insert_func(flags, alloc)); }
|
|
|
|
/**
|
|
* Remove translations that overlap with a given virtual region
|
|
*
|
|
* \param vo region offset within the tables virtual region
|
|
* \param size region size
|
|
* \param alloc second level translation table allocator
|
|
*/
|
|
void remove_translation(addr_t vo, size_t size, Allocator & alloc)
|
|
{
|
|
_range_op(vo, 0, size, Remove_func(alloc));
|
|
}
|
|
} __attribute__((aligned(1 << ALIGNM_LOG2)));
|
|
|
|
|
|
class Hw::Page_table : public Pml4_table
|
|
{
|
|
public:
|
|
|
|
using Pml4_table::Pml4_table;
|
|
|
|
enum {
|
|
TABLE_LEVEL_X_SIZE_LOG2 = SIZE_LOG2_4KB,
|
|
CORE_VM_AREA_SIZE = 1024 * 1024 * 1024,
|
|
CORE_TRANS_TABLE_COUNT =
|
|
_count(CORE_VM_AREA_SIZE, SIZE_LOG2_512GB)
|
|
+ _count(CORE_VM_AREA_SIZE, SIZE_LOG2_1GB)
|
|
+ _count(CORE_VM_AREA_SIZE, SIZE_LOG2_2MB)
|
|
};
|
|
};
|
|
|
|
#endif /* _SRC__LIB__HW__SPEC__X86_64__PAGE_TABLE_H_ */
|