289 lines
7.0 KiB
C++
289 lines
7.0 KiB
C++
/*
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* \brief CPU definitions for ARM 64bit
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* \author Stefan Kalkowski
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* \date 2019-05-22
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__ARM_64__CPU_H_
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#define _SRC__LIB__HW__SPEC__ARM_64__CPU_H_
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#define SYSTEM_REGISTER(sz, name, reg, ...) \
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struct name : Genode::Register<sz> \
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{ \
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static access_t read() \
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{ \
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access_t v; \
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asm volatile ("mrs %0, " #reg : "=r" (v)); \
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return v; \
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} \
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\
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static void write(access_t const v) { \
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asm volatile ("msr " #reg ", %0" :: "r" (v)); } \
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\
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__VA_ARGS__; \
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};
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namespace Hw { struct Arm_64_cpu; }
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struct Hw::Arm_64_cpu
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{
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SYSTEM_REGISTER(64, Actlr_el1, actlr_el1);
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SYSTEM_REGISTER(64, Amair_el1, amair_el1);
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SYSTEM_REGISTER(32, Ccsidr_el1, ccsidr_el1);
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SYSTEM_REGISTER(64, Clidr_el1, clidr_el1,
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enum Cache_type {
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NO_CACHE,
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INSTRUCTION_CACHE,
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DATA_CACHE,
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SEPARATE_CACHE,
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UNIFIED_CACHE
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};
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);
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SYSTEM_REGISTER(32, Csselr_el1, csselr_el1,
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struct Instr : Bitfield<0, 1> {};
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struct Level : Bitfield<1, 3> {};
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);
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SYSTEM_REGISTER(32, Cpacr_el1, cpacr_el1);
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SYSTEM_REGISTER(32, Cptr_el2, cptr_el2,
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struct Tta : Bitfield<20, 1> {}; );
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SYSTEM_REGISTER(64, Current_el, currentel,
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enum Level { EL0, EL1, EL2, EL3 };
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struct El : Bitfield<2, 2> {};
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);
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struct Esr : Genode::Register<64>
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{
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struct Ec : Bitfield<26, 6>
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{
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enum Exception {
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SVC = 0b010101,
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INST_ABORT_LOW_LEVEL = 0b100000,
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INST_ABORT_SAME_LEVEL = 0b100001,
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DATA_ABORT_LOW_LEVEL = 0b100100,
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DATA_ABORT_SAME_LEVEL = 0b100101,
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};
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};
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struct Iss : Bitfield<0, 25>
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{
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struct Abort : Register<32>
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{
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struct Level : Bitfield<0, 2> {};
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struct Fsc : Bitfield<2, 4>
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{
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enum Fault {
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ADDR_SIZE,
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TRANSLATION,
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ACCESS_FLAG,
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PERMISSION
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};
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enum Data_abort_fault { ALIGNMENT = 8 };
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};
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struct Write : Bitfield<6, 1> {};
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};
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};
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};
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SYSTEM_REGISTER(64, Esr_el1, esr_el1);
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SYSTEM_REGISTER(64, Far_el1, far_el1);
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SYSTEM_REGISTER(32, Fpcr, fpcr);
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SYSTEM_REGISTER(64, Hcr_el2, hcr_el2,
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struct Rw : Bitfield<31, 1> {};
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);
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SYSTEM_REGISTER(32, Hstr_el2, hstr_el2);
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SYSTEM_REGISTER(64, Id_aa64isar0_el1, id_aa64isar0_el1);
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SYSTEM_REGISTER(64, Id_aa64isar1_el1, id_aa64isar1_el1);
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SYSTEM_REGISTER(64, Id_aa64mmfr0_el1, id_aa64mmfr0_el1);
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SYSTEM_REGISTER(64, Id_aa64mmfr1_el1, id_aa64mmfr1_el1);
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SYSTEM_REGISTER(64, Id_aa64mmfr2_el1, id_aa64mmfr2_el1);
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SYSTEM_REGISTER(64, Id_pfr0, id_aa64pfr0_el1,
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struct El2 : Bitfield<8, 4> {};
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struct El3 : Bitfield<8, 4> {};
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);
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struct Mair : Genode::Register<64>
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{
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enum Attributes {
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DEVICE_MEMORY = 0x04,
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NORMAL_MEMORY_UNCACHED = 0x44,
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NORMAL_MEMORY_CACHED = 0xff,
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};
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struct Attr0 : Bitfield<0, 8> {};
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struct Attr1 : Bitfield<8, 8> {};
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struct Attr2 : Bitfield<16, 8> {};
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struct Attr3 : Bitfield<24, 8> {};
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};
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SYSTEM_REGISTER(64, Mair_el1, mair_el1);
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SYSTEM_REGISTER(64, Mair_el2, mair_el2);
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SYSTEM_REGISTER(64, Mpidr, mpidr_el1);
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SYSTEM_REGISTER(32, Pmcr_el0, pmcr_el0);
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SYSTEM_REGISTER(32, Pmcntenset_el0, pmcntenset_el0);
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SYSTEM_REGISTER(32, Pmuserenr_el0, pmuserenr_el0);
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SYSTEM_REGISTER(64, Scr, scr_el3,
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struct Ns : Bitfield<0, 1> {};
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struct Smd : Bitfield<7, 1> {};
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struct Rw : Bitfield<10, 1> {};
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);
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struct Sctlr : Genode::Register<64>
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{
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struct M : Bitfield<0, 1> { };
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struct A : Bitfield<1, 1> { };
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struct C : Bitfield<2, 1> { };
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struct Sa : Bitfield<3, 1> { };
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struct Sa0 : Bitfield<4, 1> { };
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struct I : Bitfield<12, 1> { };
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struct Uct : Bitfield<15, 1> { };
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struct Wxn : Bitfield<19, 1> { };
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};
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SYSTEM_REGISTER(64, Sctlr_el1, sctlr_el1);
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SYSTEM_REGISTER(64, Sctlr_el2, sctlr_el2);
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struct Spsr : Genode::Register<64>
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{
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struct Sp : Bitfield<0, 1> {};
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struct El : Bitfield<2, 2> {};
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struct F : Bitfield<6, 1> {};
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struct I : Bitfield<7, 1> {};
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struct A : Bitfield<8, 1> {};
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struct D : Bitfield<9, 1> {};
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};
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SYSTEM_REGISTER(64, Spsr_el2, spsr_el2);
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SYSTEM_REGISTER(64, Spsr_el3, spsr_el3);
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SYSTEM_REGISTER(64, Tcr_el1, tcr_el1,
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struct T0sz : Bitfield<0, 6> { };
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struct Epd0 : Bitfield<7, 1> { };
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struct Irgn0 : Bitfield<8, 2> { };
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struct Orgn0 : Bitfield<10, 2> { };
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struct Sh0 : Bitfield<12, 2> { };
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struct Tg0 : Bitfield<14, 2> { };
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struct T1sz : Bitfield<16, 6> { };
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struct A1 : Bitfield<22, 1> { };
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struct Epd1 : Bitfield<23, 1> { };
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struct Irgn1 : Bitfield<24, 2> { };
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struct Orgn1 : Bitfield<26, 2> { };
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struct Sh1 : Bitfield<28, 2> { };
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struct Tg1 : Bitfield<30, 2> { };
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struct Ips : Bitfield<32, 3> { };
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struct As : Bitfield<36, 1> { };
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);
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SYSTEM_REGISTER(64, Tcr_el2, tcr_el2,
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struct T0sz : Bitfield<0, 6> { };
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struct Irgn0 : Bitfield<8, 2> { };
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struct Orgn0 : Bitfield<10, 2> { };
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struct Sh0 : Bitfield<12, 2> { };
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);
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struct Ttbr : Genode::Register<64>
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{
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struct Baddr : Bitfield<0, 48> { };
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struct Asid : Bitfield<48, 16> { };
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};
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SYSTEM_REGISTER(64, Ttbr0_el1, ttbr0_el1);
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SYSTEM_REGISTER(64, Ttbr0_el2, ttbr0_el2);
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SYSTEM_REGISTER(64, Ttbr1_el1, ttbr1_el1);
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SYSTEM_REGISTER(64, Vbar_el1, vbar_el1);
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SYSTEM_REGISTER(64, Vbar_el2, vbar_el2);
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SYSTEM_REGISTER(32, Vtcr_el2, vtcr_el2,
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struct T0sz : Bitfield<0, 6> {};
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struct Sl0 : Bitfield<6, 2> {};
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);
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SYSTEM_REGISTER(64, Vttbr_el2, vttbr_el2,
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struct CnP : Bitfield<0, 1> { };
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struct Ba : Bitfield<1, 47> { };
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struct Asid : Bitfield<48, 8> { };
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);
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static inline unsigned current_privilege_level() {
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return Current_el::El::get(Current_el::read()); }
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/*****************************
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** Generic timer interface **
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*****************************/
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SYSTEM_REGISTER(64, Cntfrq_el0, cntfrq_el0);
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SYSTEM_REGISTER(32, Cntp_ctl_el0, cntp_ctl_el0,
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struct Enable : Bitfield<0, 1> {};
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struct Istatus : Bitfield<2, 1> {};
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);
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SYSTEM_REGISTER(64, Cntpct_el0, cntpct_el0);
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SYSTEM_REGISTER(32, Cntp_tval_el0, cntp_tval_el0);
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SYSTEM_REGISTER(32, Cntkctl_el1, cntkctl_el1);
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SYSTEM_REGISTER(32, Cnthctl_el2, cnthctl_el2);
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using Cntfrq = Cntfrq_el0;
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using Cntp_ctl = Cntp_ctl_el0;
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using Cntpct = Cntpct_el0;
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using Cntp_tval = Cntp_tval_el0;
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static inline void wait_for_xchg(volatile int * addr,
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int new_value,
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int expected_value)
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{
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asm volatile(
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/* check if load value of 'addr' is as expected */
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"1: ldxr w7, [%0] \n"
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"cmp w7, %w2 \n"
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"b.eq 2f \n"
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/* if not, wait for other CPU to send us an event */
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"wfe \n"
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"b.ne 1b \n"
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/* if yes, attempt to write 'new_value' to 'addr' */
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"2: stxr w7, %w1, [%0]\n"
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/* if write failed, restart */
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"cbnz w7, 1b \n"
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"dmb #0 \n"
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:: "r"(addr), "r"(new_value), "r"(expected_value) : "cc", "x7");
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}
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static inline void wakeup_waiting_cpus()
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{
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asm volatile(
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"dsb #0 \n"
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"sev \n"
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);
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}
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};
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#undef SYSTEM_REGISTER
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#endif /* _SRC__LIB__HW__SPEC__ARM_64__CPU_H_ */
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