107 lines
2.5 KiB
C++
107 lines
2.5 KiB
C++
/*
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* \brief ARM cpu context initialization
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* \author Stefan Kalkowski
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* \date 2017-04-12
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <util/bit_allocator.h>
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#include <base/internal/unmanaged_singleton.h>
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#include <kernel/cpu.h>
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#include <kernel/thread.h>
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#include <spec/arm/cpu_support.h>
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using namespace Genode;
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Arm_cpu::Context::Context(bool privileged)
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{
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using Psr = Arm_cpu::Psr;
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Psr::access_t v = 0;
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Psr::M::set(v, privileged ? Psr::M::SYS : Psr::M::USR);
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if (Board::Pic::fast_interrupts()) Psr::I::set(v, 1);
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else Psr::F::set(v, 1);
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Psr::A::set(v, 1);
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cpsr = v;
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cpu_exception = RESET;
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}
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using Asid_allocator = Bit_allocator<256>;
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static Asid_allocator &alloc() {
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return *unmanaged_singleton<Asid_allocator>(); }
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Arm_cpu::Mmu_context::Mmu_context(addr_t table)
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: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr::init(table)) { }
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Genode::Arm_cpu::Mmu_context::~Mmu_context()
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{
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/* flush TLB by ASID */
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Cpu::Tlbiasid::write(id());
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alloc().free(id());
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}
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using Thread_fault = Kernel::Thread_fault;
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void Arm_cpu::mmu_fault(Context & c, Thread_fault & fault)
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{
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bool prefetch = c.cpu_exception == Context::PREFETCH_ABORT;
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fault.addr = prefetch ? Ifar::read() : Dfar::read();
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Fsr::access_t fsr = prefetch ? Ifsr::read() : Dfsr::read();
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if (!prefetch && Dfsr::Wnr::get(fsr)) {
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fault.type = Thread_fault::WRITE;
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return;
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}
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Cpu::mmu_fault_status(Fsr::Fs::get(fsr), fault);
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}
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void Arm_cpu::mmu_fault_status(Fsr::access_t fsr, Thread_fault & fault)
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{
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enum {
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FAULT_MASK = 0b11101,
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TRANSLATION = 0b00101,
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PERMISSION = 0b01101,
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};
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switch(fsr & FAULT_MASK) {
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case TRANSLATION: fault.type = Thread_fault::PAGE_MISSING; return;
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case PERMISSION: fault.type = Thread_fault::EXEC; return;
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default: fault.type = Thread_fault::UNKNOWN;
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};
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}
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void Arm_cpu::switch_to(Arm_cpu::Context&, Arm_cpu::Mmu_context & o)
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{
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if (o.cidr == 0) return;
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Cidr::access_t cidr = Cidr::read();
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if (cidr != o.cidr) {
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/**
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* First switch to global mappings only to prevent
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* that wrong branch predicts result due to ASID
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* and Page-Table not being in sync (see ARM RM B 3.10.4)
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*/
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Cidr::write(0);
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Cpu::synchronization_barrier();
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Ttbr0::write(o.ttbr0);
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Cpu::synchronization_barrier();
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Cidr::write(o.cidr);
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Cpu::synchronization_barrier();
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}
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}
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