7aff1895bf
This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
36 lines
744 B
C++
36 lines
744 B
C++
/*
|
|
* \brief Kernel entrypoint for non-SMP systems
|
|
* \author Martin Stein
|
|
* \author Stefan Kalkowski
|
|
* \date 2011-10-20
|
|
*/
|
|
|
|
/*
|
|
* Copyright (C) 2011-2015 Genode Labs GmbH
|
|
*
|
|
* This file is part of the Genode OS framework, which is distributed
|
|
* under the terms of the GNU General Public License version 2.
|
|
*/
|
|
|
|
/* core includes */
|
|
#include <kernel/cpu.h>
|
|
|
|
|
|
extern "C" void kernel()
|
|
{
|
|
using namespace Kernel;
|
|
|
|
Cpu * const cpu = cpu_pool()->cpu(Cpu::executing_id());
|
|
cpu->scheduled_job().exception(cpu->id());
|
|
cpu->schedule().proceed(cpu->id());
|
|
}
|
|
|
|
|
|
void Kernel::Cpu::Ipi::occurred() { }
|
|
|
|
|
|
void Kernel::Cpu::Ipi::trigger(unsigned const cpu_id) { }
|
|
|
|
|
|
Kernel::Cpu::Ipi::Ipi(Kernel::Irq::Pool &p) : Kernel::Irq(Kernel::Pic::IPI, p) { }
|