264 lines
6.4 KiB
C++
264 lines
6.4 KiB
C++
/*
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* \brief Kernel backend for virtual machines
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* \author Stefan Kalkowski
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* \date 2015-02-10
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <platform_pd.h>
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#include <kernel/vm.h>
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namespace Kernel
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{
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Vm_pool * vm_pool() { return unmanaged_singleton<Vm_pool>(); }
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/**
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* ARM's virtual interrupt controller cpu interface
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*/
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struct Virtual_pic;
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/**
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* ARM's virtual timer counter
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*/
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struct Virtual_timer;
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/**
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* Kernel private virtualization interrupts, delivered to VM/VMMs
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*/
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struct Vm_irq;
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/**
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* Cpu-specific initialization for virtualization support
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*/
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void prepare_hypervisor(void);
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}
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using namespace Kernel;
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extern void * _vt_vm_entry;
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extern void * _vt_host_entry;
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extern Genode::addr_t _vt_vm_context_ptr;
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extern Genode::addr_t _vt_host_context_ptr;
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extern Genode::addr_t _mt_master_context_begin;
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struct Kernel::Vm_irq : Kernel::Irq
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{
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Vm_irq(unsigned const irq) : Kernel::Irq(irq, *cpu_pool()->executing_cpu()) {}
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/**
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* A VM interrupt gets injected into the VM scheduled on the current CPU
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*/
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void occurred()
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{
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Cpu_job * job = cpu_pool()->executing_cpu()->scheduled_job();
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Vm *vm = dynamic_cast<Vm*>(job);
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if (!vm)
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PERR("VM timer interrupt while VM is not runnning!");
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else
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vm->inject_irq(_id());
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}
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};
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struct Kernel::Virtual_pic : Genode::Mmio
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{
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struct Gich_hcr : Register<0x00, 32> { };
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struct Gich_vmcr : Register<0x08, 32> { };
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struct Gich_misr : Register<0x10, 32> { };
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struct Gich_eisr0 : Register<0x20, 32> { };
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struct Gich_elrsr0 : Register<0x30, 32> { };
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struct Gich_apr : Register<0xf0, 32> { };
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template <unsigned SLOT>
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struct Gich_lr : Register<0x100 + SLOT*4, 32> { };
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Vm_irq irq = Genode::Board::VT_MAINTAINANCE_IRQ;
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Virtual_pic()
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: Genode::Mmio(Genode::Board::IRQ_CONTROLLER_VT_CTRL_BASE) { }
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static Virtual_pic& pic()
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{
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static Virtual_pic vgic;
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return vgic;
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}
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/**
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* Save the virtual interrupt controller state to VM state
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*/
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static void save (Genode::Vm_state *s)
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{
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s->gic_hcr = pic().read<Gich_hcr >();
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s->gic_misr = pic().read<Gich_misr >();
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s->gic_vmcr = pic().read<Gich_vmcr >();
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s->gic_apr = pic().read<Gich_apr >();
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s->gic_eisr = pic().read<Gich_eisr0 >();
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s->gic_elrsr0 = pic().read<Gich_elrsr0>();
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s->gic_lr[0] = pic().read<Gich_lr<0> >();
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s->gic_lr[1] = pic().read<Gich_lr<1> >();
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s->gic_lr[2] = pic().read<Gich_lr<2> >();
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s->gic_lr[3] = pic().read<Gich_lr<3> >();
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/* disable virtual PIC CPU interface */
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pic().write<Gich_hcr>(0);
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}
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/**
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* Load the virtual interrupt controller state from VM state
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*/
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static void load (Genode::Vm_state *s)
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{
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pic().write<Gich_hcr >(s->gic_hcr );
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pic().write<Gich_misr >(s->gic_misr);
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pic().write<Gich_vmcr >(s->gic_vmcr);
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pic().write<Gich_apr >(s->gic_apr );
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pic().write<Gich_elrsr0>(s->gic_elrsr0);
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pic().write<Gich_lr<0> >(s->gic_lr[0]);
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pic().write<Gich_lr<1> >(s->gic_lr[1]);
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pic().write<Gich_lr<2> >(s->gic_lr[2]);
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pic().write<Gich_lr<3> >(s->gic_lr[3]);
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}
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};
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struct Kernel::Virtual_timer
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{
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Vm_irq irq = Genode::Board::VT_TIMER_IRQ;
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/**
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* Return virtual timer object of currently executing cpu
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*
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* FIXME: remove this when re-designing the CPU (issue #1252)
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*/
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static Virtual_timer& timer()
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{
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static Virtual_timer timer[NR_OF_CPUS];
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return timer[Cpu::executing_id()];
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}
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/**
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* Resets the virtual timer, thereby it disables its interrupt
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*/
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static void reset()
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{
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timer().irq.disable();
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asm volatile("mcr p15, 0, %0, c14, c3, 1 \n"
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"mcr p15, 0, %0, c14, c3, 0" :: "r" (0));
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}
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/**
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* Save the virtual timer state to VM state
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*/
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static void save(Genode::Vm_state *s)
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{
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asm volatile("mrc p15, 0, %0, c14, c3, 0 \n"
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"mrc p15, 0, %1, c14, c3, 1" :
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"=r" (s->timer_val), "=r" (s->timer_ctrl));
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}
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/**
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* Load the virtual timer state from VM state
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*/
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static void load(Genode::Vm_state *s, unsigned const cpu_id)
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{
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if (s->timer_irq) timer().irq.enable();
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asm volatile("mcr p15, 0, %0, c14, c3, 1 \n"
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"mcr p15, 0, %1, c14, c3, 0 \n"
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"mcr p15, 0, %2, c14, c3, 1" ::
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"r" (0),
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"r" (s->timer_val), "r" (s->timer_ctrl));
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}
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};
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void Kernel::prepare_hypervisor()
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{
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/* set hypervisor exception vector */
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Cpu::hyp_exception_entry_at(&_vt_host_entry);
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/* set hypervisor's translation table */
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Genode::Translation_table * table =
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core_pd()->platform_pd()->translation_table_phys();
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Cpu::Httbr::translation_table((addr_t)table);
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/* prepare MMU usage by hypervisor code */
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Cpu::Htcr::write(Cpu::Ttbcr::init_virt_kernel());
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Cpu::Hcptr::write(Cpu::Hcptr::init());
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Cpu::Hmair0::write(Cpu::Mair0::init_virt_kernel());
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Cpu::Vtcr::write(Cpu::Vtcr::init());
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Cpu::Hsctlr::write(Cpu::Sctlr::init_virt_kernel());
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/* initialize host context used in virtualization world switch */
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*((void**)&_vt_host_context_ptr) = &_mt_master_context_begin;
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}
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Kernel::Vm::Vm(void * const state,
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Kernel::Signal_context * const context,
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void * const table)
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: Cpu_job(Cpu_priority::min, 0),
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_state((Genode::Vm_state * const)state),
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_context(context),
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_table(table) {
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affinity(cpu_pool()->primary_cpu());
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Virtual_pic::pic().irq.enable();
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}
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void Kernel::Vm::exception(unsigned const cpu_id)
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{
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Virtual_timer::save(_state);
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switch(_state->cpu_exception) {
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case Genode::Cpu_state::INTERRUPT_REQUEST:
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case Genode::Cpu_state::FAST_INTERRUPT_REQUEST:
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_interrupt(cpu_id);
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break;
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default:
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pause();
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_context->submit(1);
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}
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Virtual_pic::save(_state);
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Virtual_timer::reset();
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}
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void Kernel::Vm::proceed(unsigned const cpu_id)
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{
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/*
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* the following values have to be enforced by the hypervisor
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*/
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_state->vttbr = Cpu::Ttbr0::init((Genode::addr_t)_table, id());
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/*
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* use the following report fields not needed for loading the context
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* to transport the HSTR and HCR register descriptions into the assembler
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* path in a dense way
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*/
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_state->hsr = Cpu::Hstr::init();
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_state->hpfar = Cpu::Hcr::init();
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Virtual_pic::load(_state);
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Virtual_timer::load(_state, cpu_id);
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mtc()->switch_to(reinterpret_cast<Cpu::Context*>(_state), cpu_id,
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(addr_t) &_vt_vm_entry, (addr_t)&_vt_vm_context_ptr);
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}
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void Vm::inject_irq(unsigned irq)
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{
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_state->gic_irq = irq;
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pause();
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_context->submit(1);
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}
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