c850462f43
Instead of having an ID allocator per object class use one global allocator for all. Thereby artificial limitations for the different object types are superfluent. Moreover, replace the base-hw specific id allocator implementation with the generic Bit_allocator, which is also memory saving. Ref #1443
171 lines
4.0 KiB
C++
171 lines
4.0 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <cpu.h>
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#include <kernel/pd.h>
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/**
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* Helpers that increase readability of MCR and MRC commands
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*/
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#define READ_CLIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 1\n"
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#define READ_CCSIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 0\n"
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#define WRITE_CSSELR(rs) "mcr p15, 2, " #rs ", c0, c0, 0\n"
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#define WRITE_DCISW(rs) "mcr p15, 0, " #rs ", c7, c6, 2\n"
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#define WRITE_DCCSW(rs) "mcr p15, 0, " #rs ", c7, c10, 2\n"
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/**
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* First macro to do a set/way operation on all entries of all data caches
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*
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* Must be inserted directly before the targeted operation. Returns operand
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* for targeted operation in R6.
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*/
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#define FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0 \
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\
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/* get the cache level value (Clidr::Loc) */ \
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READ_CLIDR(r0) \
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"ands r3, r0, #0x7000000\n" \
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"mov r3, r3, lsr #23\n" \
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\
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/* skip all if cache level value is zero */ \
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"beq 5f\n" \
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"mov r9, #0\n" \
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\
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/* begin loop over cache numbers */ \
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"1:\n" \
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\
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/* work out 3 x cache level */ \
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"add r2, r9, r9, lsr #1\n" \
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\
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/* get the cache type of current cache number (Clidr::CtypeX) */ \
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"mov r1, r0, lsr r2\n" \
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"and r1, r1, #7\n" \
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"cmp r1, #2\n" \
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\
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/* skip cache number if there's no data cache at this level */ \
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"blt 4f\n" \
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\
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/* select the appropriate CCSIDR according to cache level and type */ \
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WRITE_CSSELR(r9) \
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"isb\n" \
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\
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/* get the line length of current cache (Ccsidr::LineSize) */ \
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READ_CCSIDR(r1) \
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"and r2, r1, #0x7\n" \
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\
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/* add 4 for the line-length offset (log2 of 16 bytes) */ \
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"add r2, r2, #4\n" \
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\
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/* get the associativity or max way size (Ccsidr::Associativity) */ \
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"ldr r4, =0x3ff\n" \
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"ands r4, r4, r1, lsr #3\n" \
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\
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/* get the bit position of the way-size increment */ \
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"clz r5, r4\n" \
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\
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/* get a working copy of the max way size */ \
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"mov r8, r4\n" \
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\
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/* begin loop over way numbers */ \
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"2:\n" \
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\
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/* get the number of sets or the max index size (Ccsidr::NumSets) */ \
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"ldr r7, =0x00007fff\n" \
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"ands r7, r7, r1, lsr #13\n" \
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\
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/* begin loop over indices */ \
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"3:\n" \
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\
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/* factor in the way number and cache number into write value */ \
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"orr r6, r9, r8, lsl r5\n" \
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\
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/* factor in the index number into write value */ \
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"orr r6, r6, r7, lsl r2\n"
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/**
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* Second macro to do a set/way operation on all entries of all data caches
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*
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* Must be inserted directly after the targeted operation.
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*/
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#define FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1 \
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\
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/* decrement the index */ \
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"subs r7, r7, #1\n" \
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\
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/* end loop over indices */ \
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"bge 3b\n" \
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\
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/* decrement the way number */ \
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"subs r8, r8, #1\n" \
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\
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/* end loop over way numbers */ \
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"bge 2b\n" \
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\
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/* label to skip a cache number */ \
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"4:\n" \
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\
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/* increment the cache number */ \
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"add r9, r9, #2\n" \
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"cmp r3, r9\n" \
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\
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/* end loop over cache numbers */ \
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"bgt 1b\n" \
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\
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/* synchronize data */ \
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"dsb\n" \
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\
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/* label to skip all */ \
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"5:\n" \
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::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
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void Genode::Arm::flush_data_caches()
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{
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asm volatile (
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
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WRITE_DCCSW(r6)
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1);
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Board::outer_cache_flush();
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}
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void Genode::Arm::invalidate_data_caches()
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{
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asm volatile (
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
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WRITE_DCISW(r6)
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1);
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Board::outer_cache_invalidate();
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}
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Genode::Arm::Psr::access_t Genode::Arm::Psr::init_user_with_trustzone()
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{
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access_t v = 0;
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M::set(v, M::USR);
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I::set(v, 1);
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A::set(v, 1);
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return v;
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}
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void Genode::Arm_v7::init_virt_kernel(Kernel::Pd * pd)
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{
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Cidr::write(pd->asid);
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Dacr::write(Dacr::init_virt_kernel());
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Ttbr0::write(Ttbr0::init((Genode::addr_t)pd->translation_table()));
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Ttbcr::write(0);
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Sctlr::write(Sctlr::init_virt_kernel());
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inval_branch_predicts();
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}
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