1b1fd1e1f9
The new scheduler serves the orthogonal requirements of both high-throughput-oriented scheduling contexts (shortly called fill in the scheduler) and low-latency-oriented scheduling contexts (shortly called claim in the scheduler). Thus it knows two scheduling modes. Every claim owns a CPU-time-quota expressed as percentage of a super period (currently 1 second) and a priority that is absolute as long as the claim has quota left for the current super period. At the end of a super period the quota of all claims gets refreshed. During a super period, the claim mode is dominant as long as any active claim has quota left. Every time this isn't the case, the scheduler switches to scheduling of fills. Fills are scheduled in a simple round robin with identical time slices. Order and time-slices of the fill scheduling are not affected by the super period. Now on thread creation, two arguments, priority and quota are needed. If quota is 0, the new thread participates in CPU scheduling with a fill only. Otherwise he participates with both a claim and a fill. This concept dovetails nicely with Genodes quota based resource management as any process can grant subsets of its own CPU-time and priorities to its child without knowing the global means of CPU-time and priority. The commit also adds a run script that enables an automated unit test of the scheduler implementation. fix #1225
69 lines
1.4 KiB
C++
69 lines
1.4 KiB
C++
/*
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* \brief Timer driver for core
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* \author Norman Feske
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* \date 2013-04-05
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _TIMER_H_
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#define _TIMER_H_
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/* Genode includes */
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#include <util/mmio.h>
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/* core includes */
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#include <board.h>
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namespace Genode
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{
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/**
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* Timer driver for core
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*
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* Timer channel 0 apparently doesn't work on the RPI, so we use channel 1
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*/
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class Timer;
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}
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class Genode::Timer : public Mmio
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{
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private:
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struct Cs : Register<0x0, 32> { struct M1 : Bitfield<1, 1> { }; };
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struct Clo : Register<0x4, 32> { };
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struct Cmp : Register<0x10, 32> { };
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public:
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Timer() : Mmio(Board::SYSTEM_TIMER_MMIO_BASE) { }
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static unsigned interrupt_id(int) { return Board::SYSTEM_TIMER_IRQ; }
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inline void start_one_shot(uint32_t const tics, unsigned)
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{
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write<Cs::M1>(1);
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read<Cs>();
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write<Clo>(0);
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write<Cmp>(read<Clo>() + tics);
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}
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static uint32_t ms_to_tics(unsigned const ms) {
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return (Board::SYSTEM_TIMER_CLOCK / 1000) * ms; }
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unsigned value(unsigned)
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{
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Cmp::access_t const cmp = read<Cmp>();
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Clo::access_t const clo = read<Clo>();
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return cmp > clo ? cmp - clo : 0;
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}
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};
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namespace Kernel { class Timer : public Genode::Timer { }; }
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#endif /* _TIMER_H_ */
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