553 lines
17 KiB
C++
553 lines
17 KiB
C++
/*
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* \brief Image Processing Unit registers
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2012-11-10
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*/
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/*
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* Copyright (C) 2009-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_
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#define _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <util/string.h>
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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class Ipu : Genode::Mmio
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{
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private:
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enum { REGS_OFF = 0x6000000 };
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struct Conf : Register<0x0, 32> { };
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template<unsigned NR>
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struct Int_ctrl : Register<0x3c+(NR*4), 32> { };
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struct Srm_pri2 : Register<0xa4, 32>
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{
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struct Dp_m_srm : Bitfield<3,2> { enum { UPDATE_NOW = 1 }; };
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};
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struct Disp_gen : Register<0xc4, 32> { };
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struct Mem_rst : Register<0xdc, 32> { };
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struct Pm : Register<0xe0, 32> { };
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struct Gpr : Register<0xe4, 32> { };
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struct Ch_db_mode_sel0 : Register<0x150, 32> { };
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struct Alt_ch_trb_mode_sel0 : Register<0x178, 32> { };
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struct Cur_buf_0 : Register<0x23c, 32> { };
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struct Triple_cur_buf_1 : Register<0x25c, 32> { };
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struct Ch_buf0_rdy0 : Register<0x268, 32> { };
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struct Ch_buf1_rdy0 : Register<0x270, 32> { };
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/**************************************
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** Image DMA controller registers **
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**************************************/
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enum Idmac_channels {
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CHAN_DP_PRIMARY_MAIN = 23,
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CHAN_DP_PRIMARY_AUXI = 27,
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CHAN_DC_SYNC_FLOW = 28
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};
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struct Idmac_ch_en : Register_array<0x8004, 32, 32, 1>
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{
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struct Ch : Bitfield<0, 1> { };
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};
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struct Idmac_ch_pri_1 : Register<0x8014, 32> { };
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struct Idmac_wm_en : Register_array<0x801c, 32, 32, 1>
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{
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struct Ch : Bitfield<0, 1> { };
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};
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struct Idmac_ch_lock_en_1 : Register<0x8024, 32> { };
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/***********************************
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** Display processor registers **
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***********************************/
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struct Dp_com_conf : Register<0x1040000, 32> { };
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struct Dp_fg_pos_sync : Register<0x1040008, 32> { };
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struct Gr_wnd_ctl_sync : Register<0x1040004, 32> { };
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/***********************************
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** Display interface registers **
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***********************************/
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template <Genode::off_t OFF>
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struct Di
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{
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struct General : Register<OFF+0x0, 32> { };
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struct Bs_clkgen0 : Register<OFF+0x4, 32> { };
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struct Bs_clkgen1 : Register<OFF+0x8, 32> { };
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template <unsigned NR>
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struct Sync_wave_gen0 : Register<0xc+OFF+(NR*4), 32> { };
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template <unsigned NR>
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struct Sync_wave_gen1 : Register<0x30+OFF+(NR*4), 32> { };
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struct Sync_as_gen : Register<OFF+0x54, 32> { };
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template <unsigned NR>
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struct Dw_gen : Register<0x58 + OFF + (NR*4), 32> { };
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template <unsigned NR>
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struct Dw_set3 : Register<0x118 + OFF + (NR*4), 32> { };
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template <unsigned NR>
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struct Step_repeat : Register<0x148 + OFF + (NR*4), 32> { };
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struct Polarity : Register<OFF+0x164, 32> { };
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struct Scr_conf : Register<OFF+0x170, 32> { };
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};
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typedef Di<0x40000> Di0;
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typedef Di<0x48000> Di1;
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/************************************
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** Display controller registers **
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************************************/
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struct Dc_wr_ch_conf_5 : Register<0x5805c, 32> { };
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struct Dc_wr_ch_addr_5 : Register<0x58060, 32> { };
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template <unsigned NR>
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struct Dc_rl_ch_5 : Register<0x58064+(NR*4), 32> { };
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struct Dc_gen : Register<0x580d4, 32> { };
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struct Dc_disp_conf2_0 : Register<0x580e8, 32> { };
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struct Dc_disp_conf2_1 : Register<0x580ec, 32> { };
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template <unsigned NR>
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struct Dc_map_conf : Register<0x58108+(NR*4), 32> { };
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template <unsigned NR>
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struct Dc_template : Register<0x1080000+(NR*4), 32> { };
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/***********************************************
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** Display multi FIFO controller registers **
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***********************************************/
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struct Dmfc_wr_chan : Register<0x60004, 32> { };
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struct Dmfc_wr_chan_def : Register<0x60008, 32> { };
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struct Dmfc_dp_chan : Register<0x6000c, 32> { };
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struct Dmfc_dp_chan_def : Register<0x60010, 32> { };
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struct Dmfc_general_1 : Register<0x60014, 32> { };
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struct Dmfc_ic_ctrl : Register<0x6001c, 32> { };
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class Cp_mem
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{
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public:
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enum { OFFSET = 0x1000000 };
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unsigned xv : 10; /* XV Virtual Coordinate */
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unsigned yv : 9; /* YV Virtual Coordinate */
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unsigned xb : 13; /* XB inner Block Coordinate */
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unsigned yb : 12; /* YB inner Block Coordinate */
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unsigned nsb_b : 1; /* New Sub Block */
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unsigned cf : 1; /* Current Field */
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unsigned sx : 12; /* Scroll X counter */
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unsigned sy : 11; /* Scroll Y counter */
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unsigned ns : 10; /* Number of Scroll */
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unsigned sdx : 7; /* Scroll Delta X */
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unsigned sm : 10; /* Scroll Max */
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unsigned scc : 1; /* Scrolling Configuration */
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unsigned sce : 1; /* Scrolling Enable */
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unsigned sdy : 7; /* Scroll Delta Y */
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unsigned sdrx : 1; /* Scroll Horizontal Direction */
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unsigned sdry : 1; /* Scroll Vertical Direction */
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unsigned bpp : 3; /* Bits per Pixel */
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unsigned dec_sel : 2; /* Decode Address Select */
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unsigned dim : 1; /* Access Dimension */
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unsigned so : 1; /* Scan Order */
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unsigned bndm : 3; /* Band Mode */
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unsigned bm : 2; /* Block Mode */
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unsigned rot : 1; /* Rotation */
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unsigned hf : 1; /* Horizontal Flip */
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unsigned vf : 1; /* Vertical Flip */
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unsigned the : 1; /* Threshold Enable */
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unsigned cap : 1; /* Conditional Access Polarity */
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unsigned cae : 1; /* Conditional Access Enable */
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unsigned fw : 13; /* Frame Width */
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unsigned fh : 12; /* Frame Height */
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unsigned res0 : 10; /* reserved */
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Genode::uint32_t res1[3];
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unsigned eba0 : 29; /* Ext Mem Buffer 0 Address */
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unsigned eba1 : 29; /* Ext Mem Buffer 1 Address */
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unsigned ilo : 20; /* Interlace Offset */
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unsigned npb : 7; /* Number of Pixels in Whole Burst Access */
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unsigned pfs : 4; /* Pixel Format Select */
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unsigned alu : 1; /* Alpha Used */
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unsigned albm : 3; /* Alpha Channel Mapping */
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unsigned id : 2; /* AXI ID */
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unsigned th : 7; /* Threshold */
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unsigned sly : 14; /* Stride Line */
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unsigned wid0 : 3; /* Width0 */
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unsigned wid1 : 3; /* Width1 */
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unsigned wid2 : 3; /* Width2 */
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unsigned wid3 : 3; /* Width3 */
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unsigned off0 : 5; /* Offset0 */
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unsigned off1 : 5; /* Offset1 */
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unsigned off2 : 5; /* Offset2 */
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unsigned off3 : 5; /* Offset3 */
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unsigned sxys : 1; /* Select SX SY Set */
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unsigned cre : 1; /* Conditional Read Enable */
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unsigned dec_sel2 : 1; /* Decode Address Select bit[2] */
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unsigned res2 : 9; /* reserved */
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Genode::uint32_t res3[3];
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Cp_mem() { Genode::memset(this, 0, sizeof(Cp_mem)); }
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} __attribute__((packed));
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void _init_dma_channel(unsigned channel,
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Genode::uint16_t width, Genode::uint16_t height,
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Genode::uint32_t stride, Genode::addr_t phys_base)
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{
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void *dst =(void*)(base + Cp_mem::OFFSET + channel*sizeof(Cp_mem));
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Cp_mem cpmem;
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cpmem.fw = width - 1;
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cpmem.fh = height - 1;
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cpmem.sly = stride - 1;
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cpmem.eba0 = phys_base >> 3;
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cpmem.eba1 = phys_base >> 3;
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cpmem.bpp = 3; /* corresponds to 16BPP */
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cpmem.pfs = 7; /* corresponds to RGB */
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cpmem.npb = 31; /* 32 pixel per burst access */
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/* red */
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cpmem.wid0 = 4;
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cpmem.off0 = 0;
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/* green */
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cpmem.wid1 = 5;
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cpmem.off1 = 5;
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/* blue */
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cpmem.wid2 = 4; cpmem.off2 = 11;
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/* alpha */
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cpmem.wid3 = 7;
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cpmem.off3 = 16;
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Genode::memcpy(dst, (void*)&cpmem, sizeof(Cp_mem));
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}
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void _init_di0(Genode::uint16_t width, Genode::uint16_t height,
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Genode::uint32_t stride, Genode::addr_t phys_base)
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{
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/* set MCU_T to divide MCU access window into 2 */
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write<Disp_gen>(0x1600000); // ?= 0x600000
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/* link display controller events */
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write<Dc_rl_ch_5<0> >(0x5030000);
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write<Dc_rl_ch_5<2> >(0x602);
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write<Dc_rl_ch_5<4> >(0x701);
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write<Dc_rl_ch_5<0> >(0x5030000);
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write<Dc_rl_ch_5<1> >(0x0);
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write<Dc_rl_ch_5<1> >(0x0);
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write<Dc_rl_ch_5<2> >(0x602);
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write<Dc_rl_ch_5<3> >(0x0);
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write<Dc_rl_ch_5<3> >(0x0);
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write<Dc_wr_ch_conf_5>(0x2);
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write<Dc_wr_ch_addr_5>(0x0);
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write<Dc_gen>(0x84);
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/*************************
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** Display interface **
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*************************/
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/* clear DI */
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write<Di0::General>(0x200000);
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/* initialize display interface 0 */
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write<Di0::Bs_clkgen0>(0x38);
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write<Di0::Bs_clkgen1>(0x30000);
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write<Di0::Dw_gen<0> >(0x2020300);
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write<Di0::Dw_set3<0> >(0x60000);
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write<Di0::Sync_wave_gen0<0> >(0x21310000);
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write<Di0::Sync_wave_gen1<0> >(0x10000000);
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write<Di0::Sync_wave_gen0<1> >(0x21310001);
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write<Di0::Sync_wave_gen1<1> >(0x30141000);
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write<Di0::Step_repeat<0> >(0x0);
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write<Di0::Sync_wave_gen0<2> >(0x10520000);
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write<Di0::Sync_wave_gen1<2> >(0x30142000);
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write<Di0::Scr_conf>(0x20a);
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write<Di0::Sync_wave_gen0<3> >(0x3010b);
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write<Di0::Sync_wave_gen1<3> >(0x8000000);
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write<Di0::Step_repeat<1> >(0x1e00000);
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write<Di0::Sync_wave_gen0<4> >(0x10319);
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write<Di0::Sync_wave_gen1<4> >(0xa000000);
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write<Di0::Sync_wave_gen0<5> >(0x0);
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write<Di0::Sync_wave_gen1<5> >(0x0);
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write<Di0::Sync_wave_gen0<6> >(0x0);
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write<Di0::Sync_wave_gen1<6> >(0x0);
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write<Di0::Sync_wave_gen0<7> >(0x0);
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write<Di0::Sync_wave_gen1<7> >(0x0);
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write<Di0::Sync_wave_gen0<8> >(0x0);
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write<Di0::Sync_wave_gen1<8> >(0x0);
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write<Di0::Step_repeat<2> >(0x320);
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write<Di0::Step_repeat<3> >(0x0);
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write<Di0::Step_repeat<4> >(0x0);
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/* write display connection microcode */
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write<Dc_template<10> >(0x8885);
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write<Dc_template<11> >(0x380);
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write<Dc_template<12> >(0x8845);
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write<Dc_template<13> >(0x380);
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write<Dc_template<14> >(0x8805);
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write<Dc_template<15> >(0x380);
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write<Di0::General>(0x220000);
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write<Di0::Sync_as_gen>(0x2002);
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write<Di0::General>(0x200000);
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write<Di0::Sync_as_gen>(0x4002);
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write<Di0::Polarity>(0x10);
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write<Dc_disp_conf2_0>(0x320);
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/* init IDMAC channels */
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_init_dma_channel(CHAN_DP_PRIMARY_MAIN, width, height, stride, phys_base);
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_init_dma_channel(CHAN_DP_PRIMARY_AUXI, width, height, stride, phys_base);
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/* round robin for simultaneous synchronous flows from DC & DP */
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write<Dmfc_general_1>(0x3);
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/* enable DP, DI0, DC, DMFC */
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write<Conf>(0x660);
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/* use double buffer for main DMA channel */
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write<Ch_db_mode_sel0>(1 << CHAN_DP_PRIMARY_MAIN |
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1 << CHAN_DP_PRIMARY_AUXI);
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/* buffer used by DMA channel is buffer 1 */
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write<Cur_buf_0>(1 << CHAN_DP_PRIMARY_MAIN);
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write<Dc_wr_ch_conf_5>(0x82);
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/* Enable IDMAC channels */
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write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_MAIN);
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write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_AUXI);
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}
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void _init_di1(Genode::uint16_t width, Genode::uint16_t height,
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Genode::uint32_t stride, Genode::addr_t phys_base)
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{
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write<Disp_gen>(0x600000); //write<Disp_gen>(0x2400000);
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write<Dp_com_conf>(0);
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write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
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write<Dc_rl_ch_5<0> >(0x2030000);
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write<Dc_rl_ch_5<1> >(0);
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write<Dc_rl_ch_5<2> >(0x302);
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write<Dc_rl_ch_5<3> >(0);
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write<Dc_rl_ch_5<4> >(0x401);
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write<Dc_wr_ch_conf_5>(0xe);
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write<Dc_wr_ch_addr_5>(0x0);
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write<Dc_gen>(0x84);
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write<Conf>(0);
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write<Di1::General>(0x200000);
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write<Di1::General>(0x300000);
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write<Di1::Bs_clkgen0>(0x10);
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write<Di1::Bs_clkgen1>(0x10000);
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write<Pm>(0x10101010);
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write<Di1::Dw_gen<0> >(0x300);
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write<Di1::Dw_set3<0> >(0x20000);
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write<Di1::Sync_wave_gen0<0> >(0x29f90000);
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write<Di1::Sync_wave_gen1<0> >(0x10000000);
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write<Di1::Step_repeat<0> >(0x0);
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write<Di1::Sync_wave_gen0<1> >(0x29f90001);
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write<Di1::Sync_wave_gen1<1> >(0x30781000);
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write<Di1::Step_repeat<0> >(0x0);
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write<Di1::Sync_wave_gen0<2> >(0x192a0000);
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write<Di1::Sync_wave_gen1<2> >(0x30142000);
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write<Di1::Step_repeat<1> >(0x3000000);
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write<Di1::Scr_conf>(0x325);
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write<Di1::Sync_wave_gen0<3> >(0x300fb);
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write<Di1::Sync_wave_gen1<3> >(0x8000000);
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write<Di1::Step_repeat<1> >(0x3000000);
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write<Di1::Sync_wave_gen0<4> >(0x108c1);
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write<Di1::Sync_wave_gen1<4> >(0xa000000);
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write<Di1::Step_repeat<2> >(0x400);
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write<Di1::Sync_wave_gen0<6> >(0x29f90091);
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write<Di1::Sync_wave_gen1<6> >(0x30781000);
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write<Di1::Step_repeat<3> >(0x0);
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write<Di1::Sync_wave_gen0<7> >(0x192a000a);
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write<Di1::Sync_wave_gen1<7> >(0x30142000);
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write<Di1::Step_repeat<3> >(0x0);
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write<Di1::Sync_wave_gen0<5> >(0x0);
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write<Di1::Sync_wave_gen1<5> >(0x0);
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write<Di1::Sync_wave_gen0<8> >(0x0);
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write<Di1::Sync_wave_gen1<8> >(0x0);
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write<Di1::Step_repeat<4> >(0x0);
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write<Di1::Step_repeat<2> >(0x400);
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write<Di1::Sync_wave_gen0<5> >(0x90011);
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write<Di1::Sync_wave_gen1<5> >(0x4000000);
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write<Di1::Step_repeat<2> >(0x28a0400);
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write<Dc_template<4> >(0x10885);
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write<Dc_template<5> >(0x380);
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write<Dc_template<6> >(0x845);
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write<Dc_template<7> >(0x280);
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write<Dc_template<8> >(0x10805);
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write<Dc_template<9> >(0x380);
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write<Di1::General>(0x6300000);
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write<Di1::Sync_as_gen>(0x4000);
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write<Di1::Polarity>(0x10);
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write<Dc_disp_conf2_1>(0x400);
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_init_dma_channel(CHAN_DP_PRIMARY_MAIN, width, height, stride, phys_base);
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_init_dma_channel(CHAN_DP_PRIMARY_AUXI, width, height, stride, phys_base);
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/* use double buffer for main DMA channel */
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write<Ch_db_mode_sel0>(1 << CHAN_DP_PRIMARY_MAIN |
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1 << CHAN_DP_PRIMARY_AUXI);
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/* buffer used by DMA channel is buffer 1 */
|
|
write<Cur_buf_0>(1 << CHAN_DP_PRIMARY_MAIN);
|
|
|
|
write<Conf>(0x6a0);
|
|
|
|
/* Enable IDMAC channels */
|
|
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_MAIN);
|
|
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_AUXI);
|
|
|
|
write<Idmac_wm_en>(1 << CHAN_DP_PRIMARY_MAIN |
|
|
1 << CHAN_DP_PRIMARY_AUXI);
|
|
|
|
write<Dc_wr_ch_conf_5>(0x8e);
|
|
|
|
write<Disp_gen>(0x2600000);
|
|
}
|
|
|
|
public:
|
|
|
|
/**
|
|
* IPU initialization
|
|
*/
|
|
void init(Genode::uint16_t width, Genode::uint16_t height,
|
|
Genode::uint32_t stride, Genode::addr_t phys_base,
|
|
bool di0)
|
|
{
|
|
/* stop pixel clocks */
|
|
write<Di0::General>(0);
|
|
write<Di1::General>(0);
|
|
|
|
/* reset IPU memory buffers */
|
|
write<Mem_rst>(0x807fffff);
|
|
while (read<Mem_rst>() & 0x80000000) ;
|
|
|
|
/* initialize pixel format mappings for display controller */
|
|
write<Dc_map_conf< 0> >(0x14830820);
|
|
write<Dc_map_conf< 1> >(0x2d4920e6);
|
|
write<Dc_map_conf< 2> >(0x39ac);
|
|
write<Dc_map_conf<15> >(0xfff07ff);
|
|
write<Dc_map_conf<16> >(0x5fc17ff);
|
|
write<Dc_map_conf<17> >(0x11fc0bfc);
|
|
write<Dc_map_conf<18> >(0x17ff0fff);
|
|
write<Dc_map_conf<19> >(0x4f807ff);
|
|
write<Dc_map_conf<20> >(0xff80afc);
|
|
write<Dc_map_conf<21> >(0xdfc05fc);
|
|
write<Dc_map_conf<22> >(0x15fc);
|
|
|
|
/* clear interrupt control registers */
|
|
write<Int_ctrl<4> >(0);
|
|
write<Int_ctrl<5> >(0);
|
|
write<Int_ctrl<8> >(0);
|
|
write<Int_ctrl<9> >(0);
|
|
|
|
/* disable DMFC channel from image converter */
|
|
write<Dmfc_ic_ctrl>(0x2);
|
|
|
|
/* set DMFC FIFO for idma channels */
|
|
write<Dmfc_wr_chan>(0x90); /* channel CHAN_DC_SYNC_FLOW */
|
|
write<Dmfc_wr_chan_def>(0x202020f6);
|
|
write<Dmfc_dp_chan>(0x968a); /* channels CHAN_DP_PRIMARY_XXX */
|
|
write<Dmfc_dp_chan_def>(0x2020f6f6);
|
|
write<Dmfc_general_1>(0x3);
|
|
|
|
/* set idma channels 23, 27, 28 as high priority */
|
|
write<Idmac_ch_pri_1>(1 << CHAN_DP_PRIMARY_MAIN |
|
|
1 << CHAN_DP_PRIMARY_AUXI |
|
|
1 << CHAN_DC_SYNC_FLOW);
|
|
|
|
/*
|
|
* generate 8 AXI bursts upon the assertion of DMA request
|
|
* for our channels
|
|
*/
|
|
write<Idmac_ch_lock_en_1>(0x3f0000);
|
|
|
|
if (di0)
|
|
_init_di0(width, height, stride, phys_base);
|
|
else
|
|
_init_di1(width, height, stride, phys_base);
|
|
|
|
|
|
/************************
|
|
** overlay settings **
|
|
************************/
|
|
|
|
write<Dp_com_conf>(1 << 0);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
|
|
write<Dp_fg_pos_sync>(16);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
|
|
write<Dp_com_conf>(1 << 0 | 1 << 2);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
|
|
write<Gr_wnd_ctl_sync>(0xff000000);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
}
|
|
|
|
|
|
void overlay(Genode::addr_t phys_base, int x, int y, int alpha)
|
|
{
|
|
volatile Genode::uint32_t *ptr = (volatile Genode::uint32_t*)
|
|
(base + Cp_mem::OFFSET + CHAN_DP_PRIMARY_AUXI*sizeof(Cp_mem));
|
|
ptr[8] = (((phys_base >> 3) & 0b111) << 29) | (phys_base >> 3);
|
|
ptr[9] = (phys_base >> 6);
|
|
|
|
write<Dp_fg_pos_sync>(x << 16 | y);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
|
|
write<Gr_wnd_ctl_sync>(alpha << 24);
|
|
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
|
}
|
|
|
|
|
|
/**
|
|
* Constructor
|
|
*
|
|
* \param mmio_base base address of IPU
|
|
*/
|
|
Ipu(Genode::addr_t mmio_base) : Genode::Mmio(mmio_base + REGS_OFF) { }
|
|
};
|
|
|
|
#endif /* _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_ */
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