de06eefbac
rm_fault.run triggers write on read-only ROM provided by core, which fails without this patch: arm - "raised unhandled data abort" x86 - (silent/invisible) busy loop because write fault gets never resolved
276 lines
6.7 KiB
C++
276 lines
6.7 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__CORTEX_A15__CPU_H_
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#define _CORE__SPEC__CORTEX_A15__CPU_H_
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/* core includes */
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#include <spec/arm_v7/cpu_support.h>
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namespace Genode { class Cpu; }
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class Genode::Cpu : public Arm_v7_cpu
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{
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public:
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/**
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* Translation table base register 0 (64-bit format)
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*/
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struct Ttbr0 : Ttbr0_64bit
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table, unsigned const id)
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{
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access_t v = Ttbr_64bit::Ba::masked((access_t)table);
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Ttbr_64bit::Asid::set(v, id);
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return v;
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}
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static Genode::uint32_t init(addr_t const table) {
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return table; }
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};
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/*********************************
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** Virtualization extensions **
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*********************************/
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/**
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* Hypervisor system trap register
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*/
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struct Hstr : Register<32>
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{
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/* System coprocessor primary register access trap */
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template <unsigned R>
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struct T : Bitfield<R, 1> {};
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static access_t init()
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{
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/*
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* allow cache (7), TLB (8) maintenance, and performance
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* monitor (9), process/thread ID register (13) and timer (14)
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* access.
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*/
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access_t v = 0;
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T<0>::set(v, 1);
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T<1>::set(v, 1);
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T<2>::set(v, 1);
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T<3>::set(v, 1);
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T<5>::set(v, 1);
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T<6>::set(v, 1);
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T<10>::set(v, 1);
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T<11>::set(v, 1);
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T<12>::set(v, 1);
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T<15>::set(v, 1);
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return v;
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};
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};
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/**
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* Hypervisor control register
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*/
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struct Hcr : Register<32>
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{
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struct Vm : Bitfield<0, 1> {}; /* VT MMU enabled */
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struct Fmo : Bitfield<3, 1> {}; /* FIQ cannot been masked */
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struct Imo : Bitfield<4, 1> {}; /* IRQ cannot been masked */
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struct Amo : Bitfield<5, 1> {}; /* A bit cannot been masked */
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struct Twi : Bitfield<13, 1> {}; /* trap on WFI instruction */
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struct Twe : Bitfield<14, 1> {}; /* trap on WFE instruction */
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struct Tidcp : Bitfield<20, 1> {}; /* trap lockdown */
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struct Tac : Bitfield<21, 1> {}; /* trap ACTLR accesses */
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struct Tvm : Bitfield<26, 1> {}; /* trap virtual memory ctrls */
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static access_t init()
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{
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access_t v = 0;
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Vm::set(v, 1);
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Fmo::set(v, 1);
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Imo::set(v, 1);
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Amo::set(v, 1);
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Twi::set(v, 1);
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Twe::set(v, 1);
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Tidcp::set(v, 1);
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Tac::set(v, 1);
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Tvm::set(v, 1);
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return v;
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};
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};
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/**
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* Extend basic CPU state by members relevant for 'base-hw' only
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*
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* Note: this class redefines Genode::Arm::Context
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*/
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struct Context : Genode::Cpu_state
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{
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Ttbr0::access_t ttbr0 = 0;
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addr_t sctlr = 0;
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addr_t ttbrc = 0;
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addr_t mair0 = 0;
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/**
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* Return base of assigned translation table
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*/
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addr_t translation_table() const {
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return Ttbr_64bit::Ba::masked(ttbr0); }
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/**
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* Assign translation-table base 'table'
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*/
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void translation_table(addr_t const table) {
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Ttbr_64bit::Ba::set(ttbr0, (Ttbr_64bit::access_t)(table >> 5)); }
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/**
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* Assign protection domain
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*/
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void protection_domain(Genode::uint8_t const id) {
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Ttbr_64bit::Asid::set(ttbr0, id); }
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};
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/**
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* An usermode execution state
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*
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* FIXME: this class largely overlaps with Genode::Arm::User_context
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*/
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struct User_context : Context
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{
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User_context()
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{
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Psr::access_t v = 0;
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Psr::M::set(v, Psr::M::USR);
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Psr::F::set(v, 1);
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Psr::A::set(v, 1);
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cpsr = v;
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}
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/**
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* Support for kernel calls
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*/
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void user_arg_0(unsigned const arg) { r0 = arg; }
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void user_arg_1(unsigned const arg) { r1 = arg; }
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void user_arg_2(unsigned const arg) { r2 = arg; }
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void user_arg_3(unsigned const arg) { r3 = arg; }
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void user_arg_4(unsigned const arg) { r4 = arg; }
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void user_arg_5(unsigned const arg) { r5 = arg; }
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void user_arg_6(unsigned const arg) { r6 = arg; }
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void user_arg_7(unsigned const arg) { r7 = arg; }
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unsigned user_arg_0() const { return r0; }
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unsigned user_arg_1() const { return r1; }
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unsigned user_arg_2() const { return r2; }
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unsigned user_arg_3() const { return r3; }
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unsigned user_arg_4() const { return r4; }
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unsigned user_arg_5() const { return r5; }
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unsigned user_arg_6() const { return r6; }
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unsigned user_arg_7() const { return r7; }
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/**
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* Initialize thread context
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*
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* \param table physical base of appropriate translation table
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* \param pd_id kernel name of appropriate protection domain
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*/
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void init_thread(addr_t const table, unsigned const pd_id)
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{
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protection_domain(pd_id);
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translation_table(table);
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}
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/**
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* Return if the context is in a page fault due to translation miss
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*
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* \param va holds the virtual fault-address if call returns 1
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* \param w holds wether it's a write fault if call returns 1
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*/
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bool in_fault(addr_t & va, addr_t & w) const
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{
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/* permission fault on page, 2nd level */
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static constexpr Fsr::access_t permission = 0b1111;
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switch (cpu_exception) {
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case PREFETCH_ABORT:
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{
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/* check if fault was caused by a translation miss */
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Fsr::access_t const fs = Fsr::Fs::get(Ifsr::read());
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if ((fs & 0b11100) != 0b100) return false;
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/* fetch fault data */
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w = 0;
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va = ip;
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return true;
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}
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case DATA_ABORT:
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{
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/* check if fault was caused by translation miss */
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Fsr::access_t const fs = Fsr::Fs::get(Dfsr::read());
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if ((fs != permission) && (fs & 0b11100) != 0b100)
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return false;
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/* fetch fault data */
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Dfsr::access_t const dfsr = Dfsr::read();
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w = Dfsr::Wnr::get(dfsr);
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va = Dfar::read();
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return true;
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}
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default:
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return false;
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};
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}
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};
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); }
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id();
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/**
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* Write back dirty cache lines and invalidate all cache lines
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*/
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void clean_invalidate_data_cache() {
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clean_invalidate_inner_data_cache(); }
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/**
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* Invalidate all cache lines
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*/
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void invalidate_data_cache() {
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invalidate_inner_data_cache(); }
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/*************
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** Dummies **
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*************/
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void switch_to(User_context&) { }
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bool retry_undefined_instr(Context&) { return false; }
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};
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#endif /* _CORE__SPEC__CORTEX_A15__CPU_H_ */
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