63 lines
1.9 KiB
C++
63 lines
1.9 KiB
C++
/*
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* \brief GICv3 interrupt controller for core
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* \author Sebastian Sumpf
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* \date 2019-07-08
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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Hw::Pic::Pic()
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: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
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_redistr(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE),
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_redistr_sgi(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE +
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Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_SIZE / 2),
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_max_irq(_distr.max_irq())
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{
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/* disable device */
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_distr.write<Distributor::Ctlr>(0);
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_distr.wait_for_rwp();
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/* XXX: remove */
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struct Affinity : Genode::Register<64>
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{
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struct Aff0 : Bitfield<0, 8> { };
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struct Aff1 : Bitfield<8, 8> { };
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struct Aff2 : Bitfield<16, 8> { };
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struct Aff3 : Bitfield<32, 8> { };
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};
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Genode::uint64_t mpidr = 0;
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asm volatile ("mrs %0, mpidr_el1" : "=r"(mpidr) : : "memory");
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Affinity::access_t affinity = 0;
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Affinity::Aff0::set(affinity, mpidr);
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Affinity::Aff1::set(affinity, (mpidr >> 8) & 0xff);
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Affinity::Aff2::set(affinity, (mpidr >> 16) & 0xff);
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Affinity::Aff3::set(affinity, (mpidr >> 32) & 0xff);
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/* configure every shared peripheral interrupt */
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for (unsigned i = min_spi; i <= _max_irq; i++) {
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_distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
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_distr.write<Distributor::Ipriorityr::Priority>(0xa0, i);
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_distr.write<Distributor::Icenabler::Clear_enable>(1, i);
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_distr.write<Distributor::Icpendr::Clear_pending>(1, i);
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_distr.write<Distributor::Igroup0r::Group1>(1, i);
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/* XXX remove: route all SPIs to this PE */
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_distr.write<Distributor::Irouter>(affinity, i);
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}
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/* enable device GRP1_NS with affinity */
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Distributor::Ctlr::access_t ctlr = 0;
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Distributor::Ctlr::Enable_grp1_a::set(ctlr, 1);
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Distributor::Ctlr::Are_ns::set(ctlr, 1);
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_distr.write<Distributor::Ctlr>(ctlr);
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_distr.wait_for_rwp();
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}
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