ec6c19a487
The memory barrier prevents the compiler from changing the program order of memory accesses in such a way that accesses to the guarded resource get outside the guarded stage. As cmpxchg() defines the start of the guarded stage it also represents an effective memory barrier. On x86, the architecture ensures to not reorder writes with older reads, writes to memory with other writes (except in cases that are not relevant for our locks), or read/write instructions with I/O instructions, locked instructions, and serializing instructions. However on ARM, the architectural memory model allows not only that memory accesses take local effect in another order as their program order but also that different observers (components that can access memory like data-busses, TLBs and branch predictors) observe these effects each in another order. Thus, a correct program order isn't sufficient for a correct observation order. An additional architectural preservation of the memory barrier is needed to achieve this. Fixes #692
37 lines
1.1 KiB
C++
37 lines
1.1 KiB
C++
/*
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* \brief Memory barrier
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* \author Martin Stein
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* \date 2014-11-12
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*
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* The memory barrier prevents memory accesses from being reordered in such a
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* way that accesses to the guarded resource get outside the guarded stage. As
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* cmpxchg() defines the start of the guarded stage it also represents an
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* effective memory barrier.
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*
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* On x86, the architecture ensures to not reorder writes with older reads,
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* writes to memory with other writes (except in cases that are not relevant
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* for our locks), or read/write instructions with I/O instructions, locked
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* instructions, and serializing instructions. Thus, a compiler memory-barrier
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* is sufficient.
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*/
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/*
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* Copyright (C) 2014 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__X86__CPU__MEMORY_BARRIER_H_
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#define _INCLUDE__X86__CPU__MEMORY_BARRIER_H_
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namespace Genode {
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static inline void memory_barrier()
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{
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asm volatile ("" ::: "memory");
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}
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}
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#endif /* _INCLUDE__X86__CPU__MEMORY_BARRIER_H_ */
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