102 lines
2.2 KiB
ArmAsm
102 lines
2.2 KiB
ArmAsm
/*
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* \brief Startup code for bootstrap
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* \author Stefan Kalkowski
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* \date 2016-09-22
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*/
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/*
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* Copyright (C) 2016-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.set STACK_SIZE, 4 * 16 * 1024
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.section ".text.crt0"
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.global _start
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_start:
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/***************************
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** Zero-fill BSS segment **
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***************************/
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adr r0, _bss_local_start
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adr r1, _bss_local_end
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ldr r0, [r0]
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ldr r1, [r1]
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mov r2, #0
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1:
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cmp r1, r0
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ble 2f
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str r2, [r0]
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add r0, r0, #4
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b 1b
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2:
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/*****************************************************
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** Setup multiprocessor-aware kernel stack-pointer **
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*****************************************************/
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mov sp, #0 /* for boot cpu use id 0 */
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cps #31 /* change to system mode */
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.global _start_setup_stack /* entrypoint for all cpus */
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_start_setup_stack:
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mrs r2, cpsr
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cmp r2, #31 /* check for system mode */
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mrcne p15, 0, sp, c0, c0, 5 /* read multiprocessor affinity register */
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andne sp, sp, #0xff /* set cpu id for non-boot cpu */
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cps #19 /* change to supervisor mode */
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adr r0, _start_stack /* load stack address into r0 */
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adr r1, _start_stack_size /* load stack size per cpu into r1 */
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ldr r1, [r1]
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add sp, #1 /* calculate stack start for CPU */
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mul r1, r1, sp
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add sp, r0, r1
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/****************
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** Enable VFP **
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****************/
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mov r0, #0xf
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lsl r0, #20
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mcr p15, 0, r0, c1, c0, 2 /* write to CPACR to enable VFP access */
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mcr p15, 0, r0, c7, c5, 4 /* deprecated ISB instruction <= ARMv6 */
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vmrs r0, fpexc /* enable the VFP by read/write fpexc */
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mov r1, #1 /* enable bit 30 */
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lsl r1, #30
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orr r0, r1
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vmsr fpexc, r0
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/************************************
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** Jump to high-level entry point **
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************************************/
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b init
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_bss_local_start:
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.long _bss_start
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_bss_local_end:
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.long _bss_end
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_start_stack_size:
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.long STACK_SIZE
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.align 3
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_start_stack:
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.rept NR_OF_CPUS
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.space STACK_SIZE
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.endr
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