410 lines
9.9 KiB
C++
410 lines
9.9 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PROCESSOR_DRIVER__ARM_V7_H_
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#define _PROCESSOR_DRIVER__ARM_V7_H_
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/* core includes */
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#include <processor_driver/arm.h>
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#include <board.h>
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/**
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* Helpers that increase readability of MCR and MRC commands
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*/
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#define READ_CLIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 1\n"
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#define READ_CCSIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 0\n"
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#define WRITE_CSSELR(rs) "mcr p15, 2, " #rs ", c0, c0, 0\n"
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#define WRITE_DCISW(rs) "mcr p15, 0, " #rs ", c7, c6, 2\n"
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#define WRITE_DCCSW(rs) "mcr p15, 0, " #rs ", c7, c10, 2\n"
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/**
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* First macro to do a set/way operation on all entries of all data caches
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*
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* Must be inserted directly before the targeted operation. Returns operand
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* for targeted operation in R6.
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*/
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#define FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0 \
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\
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/* get the cache level value (Clidr::Loc) */ \
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READ_CLIDR(r0) \
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"ands r3, r0, #0x7000000\n" \
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"mov r3, r3, lsr #23\n" \
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\
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/* skip all if cache level value is zero */ \
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"beq 5f\n" \
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"mov r9, #0\n" \
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\
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/* begin loop over cache numbers */ \
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"1:\n" \
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\
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/* work out 3 x cache level */ \
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"add r2, r9, r9, lsr #1\n" \
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\
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/* get the cache type of current cache number (Clidr::CtypeX) */ \
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"mov r1, r0, lsr r2\n" \
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"and r1, r1, #7\n" \
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"cmp r1, #2\n" \
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\
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/* skip cache number if there's no data cache at this level */ \
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"blt 4f\n" \
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\
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/* select the appropriate CCSIDR according to cache level and type */ \
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WRITE_CSSELR(r9) \
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"isb\n" \
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\
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/* get the line length of current cache (Ccsidr::LineSize) */ \
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READ_CCSIDR(r1) \
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"and r2, r1, #0x7\n" \
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\
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/* add 4 for the line-length offset (log2 of 16 bytes) */ \
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"add r2, r2, #4\n" \
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\
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/* get the associativity or max way size (Ccsidr::Associativity) */ \
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"ldr r4, =0x3ff\n" \
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"ands r4, r4, r1, lsr #3\n" \
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\
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/* get the bit position of the way-size increment */ \
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"clz r5, r4\n" \
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\
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/* get a working copy of the max way size */ \
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"mov r8, r4\n" \
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\
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/* begin loop over way numbers */ \
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"2:\n" \
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\
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/* get the number of sets or the max index size (Ccsidr::NumSets) */ \
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"ldr r7, =0x00007fff\n" \
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"ands r7, r7, r1, lsr #13\n" \
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\
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/* begin loop over indices */ \
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"3:\n" \
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\
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/* factor in the way number and cache number into write value */ \
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"orr r6, r9, r8, lsl r5\n" \
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\
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/* factor in the index number into write value */ \
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"orr r6, r6, r7, lsl r2\n"
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/**
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* Second macro to do a set/way operation on all entries of all data caches
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*
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* Must be inserted directly after the targeted operation.
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*/
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#define FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1 \
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\
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/* decrement the index */ \
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"subs r7, r7, #1\n" \
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\
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/* end loop over indices */ \
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"bge 3b\n" \
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\
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/* decrement the way number */ \
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"subs r8, r8, #1\n" \
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\
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/* end loop over way numbers */ \
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"bge 2b\n" \
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\
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/* label to skip a cache number */ \
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"4:\n" \
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\
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/* increment the cache number */ \
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"add r9, r9, #2\n" \
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"cmp r3, r9\n" \
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\
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/* end loop over cache numbers */ \
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"bgt 1b\n" \
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\
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/* synchronize data */ \
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"dsb\n" \
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\
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/* label to skip all */ \
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"5:\n" \
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::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
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namespace Arm_v7
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{
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using namespace Genode;
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/**
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* CPU driver for core
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*/
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struct Processor_driver : Arm::Processor_driver
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{
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/**
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* Secure configuration register
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*/
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struct Scr : Register<32>
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{
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struct Ns : Bitfield<0, 1> { }; /* not secure */
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/**
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* Read register value
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*/
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %[v], c1, c1, 0" : [v]"=r"(v) ::);
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return v;
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}
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};
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/**
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* Non-secure access control register
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*/
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struct Nsacr : Register<32>
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{
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/************************************************
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** Coprocessor 0-13 non-secure acccess enable **
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************************************************/
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struct Cpnsae10 : Bitfield<10, 1> { };
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struct Cpnsae11 : Bitfield<11, 1> { };
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};
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/**
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* System control register
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*/
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struct Sctlr : Arm::Processor_driver::Sctlr
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{
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struct Unused_0 : Bitfield<3,4> { }; /* shall be ~0 */
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struct Sw : Bitfield<10,1> { }; /* support SWP and SWPB */
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struct Unused_1 : Bitfield<16,1> { }; /* shall be ~0 */
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struct Ha : Bitfield<17,1> { }; /* enable HW access flag */
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struct Unused_2 : Bitfield<18,1> { }; /* shall be ~0 */
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struct Unused_3 : Bitfield<22,2> { }; /* shall be ~0 */
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struct Nmfi : Bitfield<27,1> { }; /* FIQs are non-maskable */
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struct Tre : Bitfield<28,1> { }; /* remap TEX[2:1] for OS */
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struct Afe : Bitfield<29,1> /* translation access perm. mode */
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{
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enum { FULL_RANGE_OF_PERMISSIONS = 0 };
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};
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struct Te : Bitfield<30,1> { }; /* do exceptions in Thumb state */
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/**
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* Static base value
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*/
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static access_t base_value()
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{
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return Unused_0::bits(~0) |
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Unused_1::bits(~0) |
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Unused_2::bits(~0) |
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Unused_3::bits(~0);
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}
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/**
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* Value for the first kernel run
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*/
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static access_t init_phys_kernel()
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{
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return base_value() |
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Arm::Processor_driver::Sctlr::init_phys_kernel() |
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Sw::bits(0) |
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Ha::bits(0) |
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Nmfi::bits(0) |
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Tre::bits(0);
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}
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/**
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* Value for the switch to virtual mode in kernel
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*/
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static access_t init_virt_kernel()
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{
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return base_value() |
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Arm::Processor_driver::Sctlr::init_virt_kernel() |
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Sw::bits(0) |
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Ha::bits(0) |
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Nmfi::bits(0) |
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Tre::bits(0);
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}
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};
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/**
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* Translation table base register 0
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*/
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struct Ttbr0 : Arm::Processor_driver::Ttbr0
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{
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struct Nos : Bitfield<5,1> { }; /* not outer shareable */
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struct Irgn_1 : Bitfield<0,1> { }; /* inner cachable mode */
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struct Irgn_0 : Bitfield<6,1> { }; /* inner cachable mode */
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/**
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* Value for the switch to virtual mode in kernel
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*
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* \param sect_table pointer to initial section table
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*/
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static access_t init_virt_kernel(addr_t const sect_table)
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{
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return Arm::Processor_driver::Ttbr0::init_virt_kernel(sect_table) |
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Nos::bits(0) |
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Irgn_1::bits(0) |
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Irgn_0::bits(1);
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}
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};
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/**
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* Translation table base control register
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*/
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struct Ttbcr : Arm::Processor_driver::Ttbcr
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{
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struct Pd0 : Bitfield<4,1> { }; /* disable walk for TTBR0 */
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struct Pd1 : Bitfield<5,1> { }; /* disable walk for TTBR1 */
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/**
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* Value for the switch to virtual mode in kernel
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*/
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static access_t init_virt_kernel()
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{
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return Arm::Processor_driver::Ttbcr::init_virt_kernel() |
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Pd0::bits(0) |
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Pd1::bits(0);
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}
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};
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/**
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* Switch to the virtual mode in kernel
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*
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* \param section_table section translation table of the initial
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* address space this function switches to
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* \param process_id process ID of the initial address space
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*/
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static void init_virt_kernel(addr_t const section_table,
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unsigned const process_id)
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{
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Cidr::write(process_id);
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Dacr::write(Dacr::init_virt_kernel());
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Ttbr0::write(Ttbr0::init_virt_kernel(section_table));
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Ttbcr::write(Ttbcr::init_virt_kernel());
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Sctlr::write(Sctlr::init_virt_kernel());
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}
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/**
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* Configure this module appropriately for the first kernel run
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*/
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static void init_phys_kernel()
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{
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Board::prepare_kernel();
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Sctlr::write(Sctlr::init_phys_kernel());
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Psr::write(Psr::init_kernel());
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flush_tlb();
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}
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/**
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* Wether we are in secure mode
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*/
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static bool secure_mode()
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{
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if (!Board::SECURITY_EXTENSION) return 0;
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return !Scr::Ns::get(Scr::read());
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}
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/******************************
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** Trustzone specific API **
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******************************/
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/**
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* Set the exception-vector's base-address for the monitor mode
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* software stack.
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*
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* \param addr address of the exception vector's base
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*/
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static inline void mon_exception_entry_at(addr_t const addr)
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{
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asm volatile ("mcr p15, 0, %[rd], c12, c0, 1" : : [rd] "r" (addr));
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}
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/**
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* Enable access of co-processors cp10 and cp11 from non-secure mode.
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*/
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static inline void allow_coprocessor_nonsecure()
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{
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Nsacr::access_t rd = Nsacr::Cpnsae10::bits(1) |
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Nsacr::Cpnsae11::bits(1);
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asm volatile ("mcr p15, 0, %[rd], c1, c1, 2" : : [rd] "r" (rd));
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}
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/**
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* Invalidate all predictions about the future control-flow
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*/
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static void invalidate_control_flow_predictions()
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{
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asm volatile ("mcr p15, 0, r0, c7, c5, 6");
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}
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/**
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* Finish all previous data transfers
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*/
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static void data_synchronization_barrier() { asm volatile ("dsb"); }
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/**
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* Enable secondary processors that loop on wait-for-event
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*
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* \param ip initial instruction pointer for secondary processors
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*/
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static void start_secondary_processors(void * const ip)
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{
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if (PROCESSORS > 1) {
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Genode::Board::secondary_processors_ip(ip);
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data_synchronization_barrier();
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asm volatile ("sev\n");
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}
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}
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/**
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* Wait for the next interrupt as cheap as possible
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*/
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static void wait_for_interrupt() { asm volatile ("wfi"); }
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};
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}
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/***************************
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** Arm::Processor_driver **
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***************************/
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void Arm::Processor_driver::flush_data_caches()
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{
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asm volatile (
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
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WRITE_DCCSW(r6)
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1);
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}
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void Arm::Processor_driver::invalidate_data_caches()
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{
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asm volatile (
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_0
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WRITE_DCISW(r6)
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FOR_ALL_SET_WAY_OF_ALL_DATA_CACHES_1);
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}
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Arm::Processor_driver::Psr::access_t Arm::Processor_driver::Psr::init_user_with_trustzone()
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{
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return M::bits(M::USER) |
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T::bits(T::ARM) |
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F::bits(0) |
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I::bits(1) |
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A::bits(1) |
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E::bits(E::LITTLE) |
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J::bits(J::ARM);
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}
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#endif /* _PROCESSOR_DRIVER__ARM_V7_H_ */
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