73 lines
1.7 KiB
C++
73 lines
1.7 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and i.MX31
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* \author Norman Feske
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* \date 2012-08-30
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <platform.h>
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#include <board.h>
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#include <pic.h>
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#include <cpu.h>
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using namespace Genode;
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/*
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* The address range below 0x30000000 is used for secure ROM, ROM, and
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* internal RAM.
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*/
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{ 0x30000000, 0x50000000 },
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/*
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* The address range between 0x8000000 and 0x9fffffff is designated for
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* SDRAM. The remaining address range is populated with peripherals.
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*/
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{ 0xa0000000, 0x24000000 }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* core UART */
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{ Board::UART_1_MMIO_BASE, Board::UART_1_MMIO_SIZE },
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/* core timer */
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{ Board::EPIT_1_MMIO_BASE, Board::EPIT_1_MMIO_SIZE },
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/* interrupt controller */
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{ Board::AVIC_MMIO_BASE, Board::AVIC_MMIO_SIZE },
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/* bus interface controller */
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{ Board::AIPS_1_MMIO_BASE, Board::AIPS_1_MMIO_SIZE },
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{ Board::AIPS_2_MMIO_BASE, Board::AIPS_2_MMIO_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Cpu::User_context::User_context() { cpsr = Psr::init_user(); }
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