70 lines
1.5 KiB
C++
70 lines
1.5 KiB
C++
/*
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* \brief Board driver definitions common to Cortex A9 SoCs
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* \author Stefan Kalkowski
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* \date 2015-02-09
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CORE__INCLUDE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_
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#define _CORE__INCLUDE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_
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/* core includes */
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#include <drivers/board_base.h>
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#include <spec/arm/pl310.h>
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namespace Cortex_a9 { class Board; }
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class Cortex_a9::Board : public Genode::Board_base
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{
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public:
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using L2_cache = Arm::Pl310;
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static constexpr bool SMP = true;
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enum Errata {
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ARM_754322,
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ARM_764369,
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ARM_775420,
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PL310_588369,
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PL310_727915,
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PL310_769419,
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};
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enum {
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/* snoop control unit */
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SCU_MMIO_BASE = CORTEX_A9_PRIVATE_MEM_BASE,
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/* interrupt controller */
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IRQ_CONTROLLER_DISTR_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
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IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
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IRQ_CONTROLLER_CPU_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x100,
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IRQ_CONTROLLER_CPU_SIZE = 0x100,
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/* timer */
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PRIVATE_TIMER_MMIO_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
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PRIVATE_TIMER_MMIO_SIZE = 0x10,
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PRIVATE_TIMER_IRQ = 29,
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};
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Board();
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L2_cache & l2_cache() { return _l2_cache; }
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void init() { }
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void wake_up_all_cpus(void * const ip);
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bool errata(Errata);
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protected:
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L2_cache _l2_cache;
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};
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#endif /* _CORE__INCLUDE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_ */
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