287 lines
6.1 KiB
C++
287 lines
6.1 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2011-10-26
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CORE__INCLUDE__SPEC__ARM_GIC__PIC_H_
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#define _CORE__INCLUDE__SPEC__ARM_GIC__PIC_H_
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/* Genode includes */
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#include <util/mmio.h>
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/* core includes */
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#include <board.h>
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namespace Genode
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{
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/**
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* Disributor of the ARM generic interrupt controller
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*/
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class Arm_gic_distributor;
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/**
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* CPU interface of the ARM generic interrupt controller
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*/
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class Arm_gic_cpu_interface;
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/**
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* Programmable interrupt controller for core
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*/
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class Pic;
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}
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namespace Kernel { using Pic = Genode::Pic; }
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class Genode::Arm_gic_distributor : public Mmio
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{
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public:
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static constexpr unsigned nr_of_irq = 1024;
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/**
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* Control register
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*/
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struct Ctlr : Register<0x000, 32>
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{
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struct Enable : Bitfield<0,1> { };
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struct Enable_grp0 : Bitfield<0,1> { };
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struct Enable_grp1 : Bitfield<1,1> { };
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};
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/**
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* Controller type register
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*/
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struct Typer : Register<0x004, 32> {
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struct It_lines_number : Bitfield<0,5> { }; };
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/**
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* Interrupt group register
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*/
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struct Igroupr : Register_array<0x80, 32, nr_of_irq, 1> {
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struct Group_status : Bitfield<0, 1> { }; };
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/**
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* Interrupt set enable registers
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*/
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struct Isenabler : Register_array<0x100, 32, nr_of_irq, 1, true> {
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struct Set_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt clear enable registers
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*/
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struct Icenabler : Register_array<0x180, 32, nr_of_irq, 1, true> {
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struct Clear_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt priority level registers
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*/
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struct Ipriorityr : Register_array<0x400, 32, nr_of_irq, 8> {
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struct Priority : Bitfield<0, 8> { }; };
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/**
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* Interrupt CPU-target registers
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*/
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struct Itargetsr : Register_array<0x800, 32, nr_of_irq, 8> {
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struct Cpu_targets : Bitfield<0, 8> { }; };
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/**
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* Interrupt configuration registers
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*/
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struct Icfgr : Register_array<0xc00, 32, nr_of_irq, 2> {
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struct Edge_triggered : Bitfield<1, 1> { }; };
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/**
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* Software generated interrupt register
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*/
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struct Sgir : Register<0xf00, 32>
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{
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struct Sgi_int_id : Bitfield<0, 4> { };
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struct Cpu_target_list : Bitfield<16, 8> { };
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struct Target_list_filter : Bitfield<24, 2>
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{
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enum Target { TARGET_LIST, ALL_OTHER, MYSELF };
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};
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};
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/**
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* Constructor
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*/
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Arm_gic_distributor(addr_t const base) : Mmio(base) { }
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/**
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* Return minimum IRQ priority
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*/
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unsigned min_priority()
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{
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write<Ipriorityr::Priority>(~0, 0);
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return read<Ipriorityr::Priority>(0);
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}
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/**
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* Return highest IRQ number
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*/
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unsigned max_irq()
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{
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constexpr unsigned line_width_log2 = 5;
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Typer::access_t const lnr = read<Typer::It_lines_number>();
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return ((lnr + 1) << line_width_log2) - 1;
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}
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};
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class Genode::Arm_gic_cpu_interface : public Mmio
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{
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public:
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/**
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* Control register
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*/
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struct Ctlr : Register<0x00, 32>
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{
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struct Enable : Bitfield<0,1> { };
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struct Enable_grp0 : Bitfield<0,1> { };
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struct Enable_grp1 : Bitfield<1,1> { };
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struct Fiq_en : Bitfield<3,1> { };
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};
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/**
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* Priority mask register
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*/
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struct Pmr : Register<0x04, 32> {
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struct Priority : Bitfield<0,8> { }; };
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/**
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* Binary point register
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*/
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struct Bpr : Register<0x08, 32> {
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struct Binary_point : Bitfield<0,3> { }; };
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/**
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* Interrupt acknowledge register
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*/
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struct Iar : Register<0x0c, 32, true> {
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struct Irq_id : Bitfield<0,10> { }; };
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/**
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* End of interrupt register
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*/
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struct Eoir : Register<0x10, 32, true> {
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struct Irq_id : Bitfield<0,10> { }; };
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/**
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* Constructor
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*/
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Arm_gic_cpu_interface(addr_t const base) : Mmio(base) { }
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};
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class Genode::Pic
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{
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public:
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enum { IPI = 1 };
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protected:
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typedef Arm_gic_cpu_interface Cpui;
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typedef Arm_gic_distributor Distr;
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static constexpr unsigned min_spi = 32;
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static constexpr unsigned spurious_id = 1023;
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Distr _distr;
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Cpui _cpui;
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Cpui::Iar::access_t _last_iar;
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unsigned const _max_irq;
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void _init();
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bool _valid(unsigned const irq_id) const { return irq_id <= _max_irq; }
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public:
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enum { NR_OF_IRQ = Distr::nr_of_irq };
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Pic();
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/**
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* Initialize CPU local interface of the controller
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*/
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void init_cpu_local();
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/**
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* Try to take an IRQ and return wether it was successful
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*
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* \param irq contains kernel name of taken IRQ on success
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*/
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bool take_request(unsigned & irq)
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{
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_last_iar = _cpui.read<Cpui::Iar>();
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irq = Cpui::Iar::Irq_id::get(_last_iar);
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return _valid(irq);
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}
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/**
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* End the last taken IRQ
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*/
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void finish_request()
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{
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_cpui.write<Cpui::Eoir>(_last_iar);
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_last_iar = Cpui::Iar::Irq_id::bits(spurious_id);
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}
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/**
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* Unmask IRQ and assign it to one CPU
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*
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* \param irq_id kernel name of targeted IRQ
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* \param cpu_id kernel name of targeted CPU
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*/
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void unmask(unsigned const irq_id, unsigned const cpu_id)
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{
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unsigned const targets = 1 << cpu_id;
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_distr.write<Distr::Itargetsr::Cpu_targets>(targets, irq_id);
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_distr.write<Distr::Isenabler::Set_enable>(1, irq_id);
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}
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/**
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* Mask IRQ with kernel name 'irq_id'
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*/
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void mask(unsigned const irq_id) {
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_distr.write<Distr::Icenabler::Clear_enable>(1, irq_id); }
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/**
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* Raise inter-processor IRQ of the CPU with kernel name 'cpu_id'
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*/
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void send_ipi(unsigned const cpu_id)
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{
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typedef Distr::Sgir Sgir;
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Sgir::access_t sgir = 0;
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Sgir::Sgi_int_id::set(sgir, IPI);
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Sgir::Cpu_target_list::set(sgir, 1 << cpu_id);
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_distr.write<Sgir>(sgir);
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}
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/**
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* Raise inter-processor interrupt on all other cores
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*/
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void send_ipi()
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{
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typedef Distr::Sgir Sgir;
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Sgir::access_t sgir = 0;
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Sgir::Sgi_int_id::set(sgir, IPI);
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Sgir::Target_list_filter::set(sgir,
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Sgir::Target_list_filter::ALL_OTHER);
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_distr.write<Sgir>(sgir);
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}
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};
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#endif /* _CORE__INCLUDE__SPEC__ARM_GIC__PIC_H_ */
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