170 lines
3.7 KiB
C++
170 lines
3.7 KiB
C++
/*
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* \brief Cpu class implementation specific to Cortex A9 SMP
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* \author Stefan Kalkowski
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* \date 2015-12-09
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*/
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/*
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* Copyright (C) 2015-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <base/log.h>
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/* core includes */
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#include <kernel/lock.h>
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#include <platform.h>
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//using namespace Kernel;
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/* entrypoint for non-boot CPUs */
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extern "C" void * _start_setup_stack;
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/**
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* SMP-safe simple counter
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*/
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class Cpu_counter
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{
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private:
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Kernel::Lock _lock;
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volatile int _value = 0;
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public:
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void inc()
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{
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Kernel::Lock::Guard guard(_lock);
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Genode::memory_barrier();
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_value++;
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}
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void wait_for(int const v) {
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while (_value < v) ; }
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};
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struct Scu : Genode::Mmio
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{
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struct Cr : Register<0x0, 32>
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{
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struct Enable : Bitfield<0, 1> { };
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};
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struct Dcr : Register<0x30, 32>
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{
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struct Bit_0 : Bitfield<0, 1> { };
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};
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struct Iassr : Register<0xc, 32>
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{
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struct Cpu0_way : Bitfield<0, 4> { };
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struct Cpu1_way : Bitfield<4, 4> { };
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struct Cpu2_way : Bitfield<8, 4> { };
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struct Cpu3_way : Bitfield<12, 4> { };
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};
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Scu(Genode::addr_t mmio) : Genode::Mmio(mmio) { }
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void invalidate()
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{
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Iassr::access_t iassr = 0;
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for (Iassr::access_t way = 0; way <= Iassr::Cpu0_way::mask();
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way++) {
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Iassr::Cpu0_way::set(iassr, way);
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Iassr::Cpu1_way::set(iassr, way);
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Iassr::Cpu2_way::set(iassr, way);
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Iassr::Cpu3_way::set(iassr, way);
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write<Iassr>(iassr);
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}
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}
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void enable(bool err_arm_764369)
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{
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if (err_arm_764369) write<Dcr::Bit_0>(1);
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write<Cr::Enable>(1);
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}
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};
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/*
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* The initialization of Cortex A9 multicore systems implies a sophisticated
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* algorithm in early revisions of this cpu.
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*
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* See ARM's Cortex-A9 MPCore TRM r2p0 in section 5.3.5 for more details
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*/
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void Platform::enable_mmu()
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{
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using Genode::Cpu;
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static volatile bool primary_cpu = true;
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static Cpu_counter data_cache_invalidated;
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static Cpu_counter data_cache_enabled;
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static Cpu_counter smp_coherency_enabled;
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bool primary = primary_cpu;
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if (primary) primary_cpu = false;
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Cpu::Sctlr::init();
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Cpu::Psr::write(Cpu::Psr::init_kernel());
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/* locally initialize interrupt controller */
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pic.init_cpu_local();
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cpu.invalidate_inner_data_cache();
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data_cache_invalidated.inc();
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/* primary cpu wakes up all others */
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if (primary && NR_OF_CPUS > 1) {
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board.wake_up_all_cpus(&_start_setup_stack);
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/* send an IPI to all other cpus */
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pic.send_ipi();
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}
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/* wait for other cores' data cache invalidation */
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data_cache_invalidated.wait_for(NR_OF_CPUS);
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if (primary) {
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Scu scu(Board::SCU_MMIO_BASE);
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scu.invalidate();
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Board::L2_cache l2_cache(Board::PL310_MMIO_BASE);
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l2_cache.disable();
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l2_cache.invalidate();
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scu.enable(board.errata(Platform::Board::ARM_764369));
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}
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/* secondary cpus wait for the primary's cache activation */
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if (!primary) data_cache_enabled.wait_for(1);
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cpu.enable_mmu_and_caches((Genode::addr_t)core_pd->table_base);
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data_cache_enabled.inc();
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cpu.clean_invalidate_inner_data_cache();
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/* wait for other cores' data cache activation */
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data_cache_enabled.wait_for(NR_OF_CPUS);
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if (primary) {
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Board::L2_cache l2_cache(board.core_mmio.virt_addr(Board::PL310_MMIO_BASE));
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l2_cache.enable();
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}
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/* secondary cpus wait for the primary's coherency activation */
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if (!primary) smp_coherency_enabled.wait_for(1);
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Cpu::Actlr::enable_smp(board);
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smp_coherency_enabled.inc();
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/*
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* strangely, some older versions (imx6) seem to not work cache coherent
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* until SMP bit is set, so write back the variable here.
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*/
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cpu.clean_invalidate_inner_data_cache();
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/* wait for other cores' coherency activation */
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smp_coherency_enabled.wait_for(NR_OF_CPUS);
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}
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