449 lines
9.9 KiB
C++
449 lines
9.9 KiB
C++
/*
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* \brief x86 CPU driver for core
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* \author Adrian-Ken Rueegsegger
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* \author Martin stein
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* \author Reto Buerki
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SPEC__X86__CPU_SUPPORT_H_
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#define _SPEC__X86__CPU_SUPPORT_H_
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/* Genode includes */
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#include <util/register.h>
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#include <kernel/interface_support.h>
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#include <cpu/cpu_state.h>
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/* base includes */
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#include <unmanaged_singleton.h>
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/* core includes */
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#include <gdt.h>
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#include <idt.h>
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#include <tss.h>
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#include <timer.h>
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extern int _mt_idt;
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extern int _mt_tss;
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namespace Genode
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{
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/**
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* Part of CPU state that is not switched on every mode transition
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*/
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class Cpu_lazy_state;
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/**
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* CPU driver for core
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*/
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class Cpu;
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}
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namespace Kernel
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{
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using Genode::Cpu_lazy_state;
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class Pd;
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}
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class Genode::Cpu_lazy_state
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{
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friend class Cpu;
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private:
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/**
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* FXSAVE area providing storage for x87 FPU, MMX, XMM, and MXCSR
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* registers.
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*
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* For further details see Intel SDM Vol. 2A, 'FXSAVE instruction'.
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*/
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char fxsave_area[527];
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/**
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* 16-byte aligned start of FXSAVE area.
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*/
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char *start;
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/**
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* Load x87 FPU State from fxsave area.
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*/
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inline void load() { asm volatile ("fxrstor %0" : : "m" (*start)); }
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/**
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* Save x87 FPU State to fxsave area.
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*/
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inline void save() { asm volatile ("fxsave %0" : "=m" (*start)); }
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public:
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/**
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* Constructor
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*
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* Calculate 16-byte aligned start of FXSAVE area if necessary.
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*/
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inline Cpu_lazy_state()
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{
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start = fxsave_area;
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if((addr_t)start & 15)
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start = (char *)((addr_t)start & ~15) + 16;
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};
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} __attribute__((aligned(16)));
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class Genode::Cpu
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{
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friend class Cpu_lazy_state;
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private:
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Idt *_idt;
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Tss *_tss;
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Cpu_lazy_state *_fpu_state;
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/**
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* Control register 0
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*/
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struct Cr0 : Register<64>
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{
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struct Pe : Bitfield<0, 1> { }; /* Protection Enable */
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struct Mp : Bitfield<1, 1> { }; /* Monitor Coprocessor */
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struct Em : Bitfield<2, 1> { }; /* Emulation */
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struct Ts : Bitfield<3, 1> { }; /* Task Switched */
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struct Et : Bitfield<4, 1> { }; /* Extension Type */
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struct Ne : Bitfield<5, 1> { }; /* Numeric Error */
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struct Wp : Bitfield<16, 1> { }; /* Write Protect */
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struct Am : Bitfield<18, 1> { }; /* Alignment Mask */
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struct Nw : Bitfield<29, 1> { }; /* Not Write-through */
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struct Cd : Bitfield<30, 1> { }; /* Cache Disable */
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struct Pg : Bitfield<31, 1> { }; /* Paging */
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static void write(access_t const v) {
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asm volatile ("mov %0, %%cr0" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr0, %0" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Disable FPU by setting the TS flag in CR0.
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*/
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static void _disable_fpu()
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{
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Cr0::write(Cr0::read() | Cr0::Ts::bits(1));
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}
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/**
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* Enable FPU by clearing the TS flag in CR0.
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*/
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static void _enable_fpu() { asm volatile ("clts"); }
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/**
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* Initialize FPU without checking for pending unmasked floating-point
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* exceptions.
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*/
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static void _init_fpu() { asm volatile ("fninit"); }
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/**
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* Returns True if the FPU is enabled.
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*/
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static bool is_fpu_enabled() { return !Cr0::Ts::get(Cr0::read()); }
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public:
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Cpu() : _fpu_state(0)
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{
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if (primary_id() == executing_id()) {
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_idt = new (&_mt_idt) Idt();
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_idt->setup(Cpu::exception_entry);
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_tss = new (&_mt_tss) Tss();
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_tss->load();
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}
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_idt->load(Cpu::exception_entry);
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_tss->setup(Cpu::exception_entry);
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}
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static constexpr addr_t exception_entry = 0xffff0000;
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static constexpr addr_t mtc_size = 1 << 13;
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/**
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* Control register 2: Page-fault linear address
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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struct Cr2 : Register<64>
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{
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struct Addr : Bitfield<0, 63> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr2, %0" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Control register 3: Page-Directory base register
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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struct Cr3 : Register<64>
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{
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struct Pwt : Bitfield<3,1> { }; /* Page-level write-through */
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struct Pcd : Bitfield<4,1> { }; /* Page-level cache disable */
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struct Pdb : Bitfield<12, 36> { }; /* Page-directory base address */
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static void write(access_t const v) {
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asm volatile ("mov %0, %%cr3" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr3, %0" : "=r" (v) :: );
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return v;
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}
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table) {
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return Pdb::masked(table); }
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};
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/**
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* Extend basic CPU state by members relevant for 'base-hw' only
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*/
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struct Context : Cpu_state
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{
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/**
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* Address of top-level paging structure.
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*/
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addr_t cr3;
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/**
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* Return base of assigned translation table
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*/
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addr_t translation_table() const { return cr3; }
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/**
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* Initialize context
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*
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* \param table physical base of appropriate translation table
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* \param core whether it is a core thread or not
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*/
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void init(addr_t const table, bool core)
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{
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/* Constants to handle IF, IOPL values */
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enum {
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EFLAGS_IF_SET = 1 << 9,
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EFLAGS_IOPL_3 = 3 << 12,
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};
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cr3 = Cr3::init(table);
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/*
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* Enable interrupts for all threads, set I/O privilege level
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* (IOPL) to 3 for core threads to allow UART access.
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*/
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eflags = EFLAGS_IF_SET;
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if (core) eflags |= EFLAGS_IOPL_3;
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else Gdt::load(Cpu::exception_entry);
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}
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};
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struct Pd {};
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/**
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* An usermode execution state
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*/
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struct User_context : Context
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{
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/**
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* Support for kernel calls
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*/
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void user_arg_0(Kernel::Call_arg const arg) { rdi = arg; }
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void user_arg_1(Kernel::Call_arg const arg) { rsi = arg; }
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void user_arg_2(Kernel::Call_arg const arg) { rdx = arg; }
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void user_arg_3(Kernel::Call_arg const arg) { rcx = arg; }
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void user_arg_4(Kernel::Call_arg const arg) { r8 = arg; }
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void user_arg_5(Kernel::Call_arg const arg) { r9 = arg; }
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void user_arg_6(Kernel::Call_arg const arg) { r10 = arg; }
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void user_arg_7(Kernel::Call_arg const arg) { r11 = arg; }
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Kernel::Call_arg user_arg_0() const { return rdi; }
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Kernel::Call_arg user_arg_1() const { return rsi; }
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Kernel::Call_arg user_arg_2() const { return rdx; }
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Kernel::Call_arg user_arg_3() const { return rcx; }
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Kernel::Call_arg user_arg_4() const { return r8; }
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Kernel::Call_arg user_arg_5() const { return r9; }
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Kernel::Call_arg user_arg_6() const { return r10; }
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Kernel::Call_arg user_arg_7() const { return r11; }
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};
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/**
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* Returns true if current execution context is running in user mode
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*/
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static bool is_user()
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{
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PDBG("not implemented");
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return false;
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}
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/**
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* Invalidate all entries of all instruction caches
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*/
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__attribute__((always_inline)) static void invalidate_instr_caches() { }
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/**
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* Flush all entries of all data caches
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*/
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inline static void flush_data_caches() { }
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/**
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* Invalidate all entries of all data caches
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*/
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inline static void invalidate_data_caches() { }
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/**
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* Flush all caches
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*/
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static void flush_caches()
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{
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flush_data_caches();
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invalidate_instr_caches();
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}
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/**
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* Invalidate all TLB entries of the address space named 'pid'
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*/
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static void flush_tlb_by_pid(unsigned const pid)
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{
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flush_caches();
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}
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/**
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* Invalidate all TLB entries
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*/
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static void flush_tlb()
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{
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flush_caches();
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}
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/**
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* Flush data-cache entries for virtual region ['base', 'base + size')
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*/
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static void
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flush_data_caches_by_virt_region(addr_t base, size_t const size) { }
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/**
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* Bin instr.-cache entries for virtual region ['base', 'base + size')
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*/
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static void
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invalidate_instr_caches_by_virt_region(addr_t base, size_t const size)
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{ }
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static void inval_branch_predicts() { };
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/**
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* Switch to the virtual mode in kernel
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*
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* \param pd kernel's pd object
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*/
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static void init_virt_kernel(Kernel::Pd * pd);
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inline static void finish_init_phys_kernel() { _init_fpu(); }
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/**
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* Configure this module appropriately for the first kernel run
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*/
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static void init_phys_kernel() { Timer::disable_pit(); };
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/**
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* Finish all previous data transfers
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*/
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static void data_synchronization_barrier() { }
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/**
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* Enable secondary CPUs with instr. pointer 'ip'
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*/
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static void start_secondary_cpus(void * const ip) { }
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/**
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* Wait for the next interrupt as cheap as possible
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*/
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static void wait_for_interrupt() { }
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/**
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* Return wether to retry an undefined user instruction after this call
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*/
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bool retry_undefined_instr(Cpu_lazy_state *) { return false; }
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/**
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* Return whether to retry an FPU instruction after this call
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*/
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bool retry_fpu_instr(Cpu_lazy_state * const state)
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{
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if (is_fpu_enabled())
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return false;
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_enable_fpu();
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if (_fpu_state != state) {
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if (_fpu_state)
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_fpu_state->save();
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state->load();
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_fpu_state = state;
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}
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return true;
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}
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return 0; }
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id() { return 0; }
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/**
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* Prepare for the proceeding of a user
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*
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* \param old_state CPU state of the last user
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* \param new_state CPU state of the next user
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*/
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static void prepare_proceeding(Cpu_lazy_state * const old_state,
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Cpu_lazy_state * const new_state)
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{
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if (old_state == new_state)
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return;
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_disable_fpu();
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}
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/*************
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** Dummies **
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*************/
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static void tlb_insertions() { inval_branch_predicts(); }
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static void translation_added(addr_t, size_t) { }
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};
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#endif /* _SPEC__X86__CPU_SUPPORT_H_ */
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