543 lines
12 KiB
C++
543 lines
12 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2012-09-11
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SPEC__ARM__CPU_SUPPORT_H_
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#define _SPEC__ARM__CPU_SUPPORT_H_
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/* Genode includes */
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#include <util/register.h>
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#include <cpu/cpu_state.h>
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/* local includes */
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#include <board.h>
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#include <util.h>
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namespace Genode
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{
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/**
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* CPU driver for core
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*/
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class Arm;
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typedef Genode::uint64_t sizet_arithm_t;
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}
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class Genode::Arm
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{
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public:
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static constexpr addr_t exception_entry = 0xffff0000;
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static constexpr addr_t mtc_size = 1 << MIN_PAGE_SIZE_LOG2;
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static constexpr addr_t data_access_align = 4;
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/**
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* Multiprocessor affinity register
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*/
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struct Mpidr : Register<32>
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{
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struct Aff_0 : Bitfield<0, 8> { }; /* affinity value 0 */
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Cache type register
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*/
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struct Ctr : Register<32>
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* System control register
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*/
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struct Sctlr : Register<32>
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{
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struct M : Bitfield<0,1> { }; /* enable MMU */
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struct C : Bitfield<2,1> { }; /* enable data cache */
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struct I : Bitfield<12,1> { }; /* enable instruction caches */
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struct V : Bitfield<13,1> { }; /* select exception entry */
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (v) :: );
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return v;
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}
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (v) : ); }
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/**
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* Do initialization that is common on value 'v'
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*/
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static void init_common(access_t & v)
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{
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C::set(v, 1);
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I::set(v, 1);
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V::set(v, 1);
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}
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/**
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* Do initialization for virtual mode in kernel on value 'v'
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*/
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static void init_virt_kernel(access_t & v) { M::set(v, 1); }
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};
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/**
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* Translation table base control register
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*/
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struct Ttbcr : Register<32>
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{
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c2, c0, 2" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Translation table base register 0
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*/
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struct Ttbr0 : Register<32>
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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struct C : Bitfield<0,1> { }; /* inner cacheable */
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struct S : Bitfield<1,1> { }; /* shareable */
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struct Rgn : Bitfield<3,2> { }; /* outer cachable mode */
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struct Nos : Bitfield<5,1> { }; /* not outer shareable */
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struct Ba : Bitfield<14, 18> { }; /* translation table base */
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/*************************************
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* with multiprocessing extension **
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*************************************/
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struct Irgn_1 : Bitfield<0,1> { };
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struct Irgn_0 : Bitfield<6,1> { };
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struct Irgn : Bitset_2<Irgn_0, Irgn_1> { }; /* inner cache mode */
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (v) :: );
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return v;
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}
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table)
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{
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access_t v = Ba::masked((addr_t)table);
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Rgn::set(v, CACHEABLE);
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S::set(v, Board::is_smp() ? 1 : 0);
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if (Board::is_smp()) Irgn::set(v, CACHEABLE);
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else C::set(v, 1);
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return v;
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}
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};
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/**
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* Domain access control register
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*/
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struct Dacr : Register<32>
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{
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struct D0 : Bitfield<0,2> { }; /* access mode for domain 0 */
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c3, c0, 0" :: "r" (v) : ); }
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/**
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* Return value initialized for virtual mode in kernel
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*/
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static access_t init_virt_kernel() { return D0::bits(1); }
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};
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/**
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* Instruction Cache Invalidate by MVA to PoU
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*/
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struct Icimvau : Register<32>
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{
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r" (v) : ); }
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};
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/**
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* Data Cache Clean and Invalidate by MVA to PoC
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*/
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struct Dccimvac : Register<32>
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{
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r" (v) : ); }
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};
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/**
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* Context identification register
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*/
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struct Cidr : Register<32>
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{
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c13, c0, 1" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c13, c0, 1" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Program status register
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*/
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struct Psr : Register<32>
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{
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/**
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* CPU mode
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*/
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struct M : Bitfield<0,5>
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{
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enum {
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USR = 16,
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SVC = 19,
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MON = 22,
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HYP = 26,
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};
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};
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struct F : Bitfield<6,1> { }; /* FIQ disable */
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struct I : Bitfield<7,1> { }; /* IRQ disable */
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struct A : Bitfield<8,1> { }; /* async. abort disable */
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static access_t read()
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{
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access_t v;
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asm volatile ("mrs %0, cpsr" : "=r" (v) :: );
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return v;
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}
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static void write(access_t const v) {
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asm volatile ("msr cpsr, %0" :: "r" (v) : ); }
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/**
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* Return value initialized for user execution with trustzone
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*/
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static access_t init_user_with_trustzone();
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/**
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* Do common initialization on register value 'v'
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*/
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static void init_common(access_t & v)
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{
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F::set(v, 1);
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A::set(v, 1);
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}
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/**
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* Return initial value for user execution
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*/
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static access_t init_user()
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{
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access_t v = 0;
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init_common(v);
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M::set(v, M::USR);
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return v;
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}
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/**
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* Return initial value for the kernel
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*/
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static access_t init_kernel()
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{
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access_t v = 0;
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init_common(v);
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M::set(v, M::SVC);
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I::set(v, 1);
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return v;
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}
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};
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/**
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* Common parts of fault status registers
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*/
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struct Fsr : Register<32>
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{
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static constexpr access_t section = 5;
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static constexpr access_t page = 7;
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struct Fs_0 : Bitfield<0, 4> { }; /* fault status */
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struct Fs_1 : Bitfield<10, 1> { }; /* fault status */
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struct Fs : Bitset_2<Fs_0, Fs_1> { }; /* fault status */
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};
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/**
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* Instruction fault status register
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*/
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struct Ifsr : Fsr
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Data fault status register
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*/
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struct Dfsr : Fsr
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{
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struct Wnr : Bitfield<11, 1> { }; /* write not read bit */
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Data fault address register
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*/
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struct Dfar : Register<32>
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{
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %[v], c6, c0, 0" : [v]"=r"(v) :: );
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return v;
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}
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};
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/**
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* Extend basic CPU state by members relevant for 'base-hw' only
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*/
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struct Context : Cpu_state
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{
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Cidr::access_t cidr;
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Ttbr0::access_t ttbr0;
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/**
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* Return base of assigned translation table
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*/
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addr_t translation_table() const {
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return Ttbr0::Ba::masked(ttbr0); }
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/**
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* Assign translation-table base 'table'
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*/
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void translation_table(addr_t const table) {
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ttbr0 = Arm::Ttbr0::init(table); }
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/**
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* Assign protection domain
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*/
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void protection_domain(Genode::uint8_t const id) { cidr = id; }
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};
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/**
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* This class comprises ARM specific protection domain attributes
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*/
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struct Pd
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{
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Genode::uint8_t asid; /* address space id */
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Pd(Genode::uint8_t id) : asid(id) {}
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};
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/**
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* An usermode execution state
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*/
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struct User_context : Context
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{
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/**
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* Constructor
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*/
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User_context();
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/**
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* Support for kernel calls
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*/
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void user_arg_0(unsigned const arg) { r0 = arg; }
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void user_arg_1(unsigned const arg) { r1 = arg; }
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void user_arg_2(unsigned const arg) { r2 = arg; }
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void user_arg_3(unsigned const arg) { r3 = arg; }
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void user_arg_4(unsigned const arg) { r4 = arg; }
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void user_arg_5(unsigned const arg) { r5 = arg; }
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void user_arg_6(unsigned const arg) { r6 = arg; }
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void user_arg_7(unsigned const arg) { r7 = arg; }
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unsigned user_arg_0() const { return r0; }
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unsigned user_arg_1() const { return r1; }
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unsigned user_arg_2() const { return r2; }
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unsigned user_arg_3() const { return r3; }
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unsigned user_arg_4() const { return r4; }
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unsigned user_arg_5() const { return r5; }
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unsigned user_arg_6() const { return r6; }
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unsigned user_arg_7() const { return r7; }
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/**
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* Initialize thread context
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*
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* \param table physical base of appropriate translation table
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* \param pd_id kernel name of appropriate protection domain
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*/
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void init_thread(addr_t const table, unsigned const pd_id)
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{
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protection_domain(pd_id);
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translation_table(table);
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}
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/**
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* Return if the context is in a page fault due to translation miss
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*
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* \param va holds the virtual fault-address if call returns 1
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* \param w holds wether it's a write fault if call returns 1
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*/
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bool in_fault(addr_t & va, addr_t & w) const
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{
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switch (cpu_exception) {
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case PREFETCH_ABORT:
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{
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/* check if fault was caused by a translation miss */
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Ifsr::access_t const fs = Ifsr::Fs::get(Ifsr::read());
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if (fs != Ifsr::section && fs != Ifsr::page)
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return false;
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/* fetch fault data */
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w = 0;
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va = ip;
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return true;
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}
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case DATA_ABORT:
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{
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/* check if fault was caused by translation miss */
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Dfsr::access_t const fs = Dfsr::Fs::get(Dfsr::read());
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if (fs != Dfsr::section && fs != Dfsr::page)
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return false;
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/* fetch fault data */
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Dfsr::access_t const dfsr = Dfsr::read();
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w = Dfsr::Wnr::get(dfsr);
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va = Dfar::read();
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return true;
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}
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default:
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return false;
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};
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}
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};
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/**
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* Returns true if current execution context is running in user mode
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*/
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static bool is_user() { return Psr::M::get(Psr::read()) == Psr::M::USR; }
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/**
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* Invalidate all entries of all instruction caches
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*/
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__attribute__((always_inline)) static void invalidate_instr_caches() {
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" :: "r" (0) : ); }
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/**
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* Flush all entries of all data caches
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*/
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static void flush_data_caches();
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/**
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* Invalidate all entries of all data caches
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*/
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static void invalidate_data_caches();
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/**
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* Flush all caches
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*/
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static void flush_caches()
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{
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flush_data_caches();
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invalidate_instr_caches();
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}
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/**
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* Invalidate all TLB entries of the address space named 'pid'
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*/
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static void flush_tlb_by_pid(unsigned const pid)
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{
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flush_caches();
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asm volatile ("mcr p15, 0, %0, c8, c7, 2" :: "r" (pid) : );
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}
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/**
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* Invalidate all TLB entries
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*/
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static void flush_tlb()
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{
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flush_caches();
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asm volatile ("mcr p15, 0, %0, c8, c7, 0" :: "r" (0) : );
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}
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static constexpr addr_t line_size = 1 << Board::CACHE_LINE_SIZE_LOG2;
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static constexpr addr_t line_align_mask = ~(line_size - 1);
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/**
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* Flush data-cache entries for virtual region ['base', 'base + size')
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*/
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static void
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flush_data_caches_by_virt_region(addr_t base, size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Dccimvac::write(base); }
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}
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/**
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* Bin instr.-cache entries for virtual region ['base', 'base + size')
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*/
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static void
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invalidate_instr_caches_by_virt_region(addr_t base, size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Icimvau::write(base); }
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}
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};
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#endif /* _SPEC__ARM__CPU_SUPPORT_H_ */
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