87 lines
1.6 KiB
C++
87 lines
1.6 KiB
C++
/*
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* \brief Board-driver base
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* \author Stefan Kalkowski
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* \date 2013-11-25
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _EXYNOS5__BOARD_BASE_H_
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#define _EXYNOS5__BOARD_BASE_H_
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namespace Genode
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{
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/**
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* Board-driver base
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*/
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class Exynos5;
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}
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class Genode::Exynos5
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{
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public:
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enum {
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/* normal RAM */
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RAM_0_BASE = 0x40000000,
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RAM_0_SIZE = 0x80000000,
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/* device IO memory */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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/* interrupt controller */
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IRQ_CONTROLLER_BASE = 0x10480000,
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IRQ_CONTROLLER_SIZE = 0x00010000,
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IRQ_CONTROLLER_VT_CTRL_BASE = 0x10484000,
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IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
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IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
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/* virtual interrupts */
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VT_MAINTAINANCE_IRQ = 25,
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VT_TIMER_IRQ = 27,
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/* UART */
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UART_2_MMIO_BASE = 0x12C20000,
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UART_2_IRQ = 85,
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/* pulse-width-modulation timer */
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PWM_MMIO_BASE = 0x12dd0000,
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PWM_MMIO_SIZE = 0x1000,
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PWM_CLOCK = 66000000,
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PWM_IRQ_0 = 68,
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/* multicore timer */
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MCT_MMIO_BASE = 0x101c0000,
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MCT_MMIO_SIZE = 0x1000,
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MCT_CLOCK = 24000000,
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MCT_IRQ_L0 = 152,
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MCT_IRQ_L1 = 153,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 6,
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/* IRAM */
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IRAM_BASE = 0x02020000,
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/* hardware name of the primary processor */
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PRIMARY_MPIDR_AFF_0 = 0,
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/* SATA/AHCI */
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SATA_IRQ = 147,
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/* SD card */
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SDMMC0_IRQ = 107,
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/* I2C */
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I2C_HDMI_IRQ = 96,
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};
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};
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#endif /* _EXYNOS5__BOARD_BASE_H_ */
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