7aff1895bf
This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
109 lines
2.2 KiB
C++
109 lines
2.2 KiB
C++
/*
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* \brief ARM with SMP support specific aspects of the kernel cpu objects
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* \author Stefan Kalkowski
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* \author Martin Stein
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* \date 2016-01-07
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*/
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/*
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* Copyright (C) 2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <kernel/cpu.h>
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namespace Kernel
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{
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/**
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* Lists all pending domain updates
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*/
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class Cpu_domain_update_list;
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}
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class Kernel::Cpu_domain_update_list
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: public Double_list_typed<Cpu_domain_update>
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{
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public:
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/**
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* Perform all pending domain updates on the executing CPU
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*/
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void do_each() {
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for_each([] (Cpu_domain_update * const u) { u->_do(); }); }
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};
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using namespace Kernel;
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/**
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* Return singleton of the CPU domain-udpate list
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*/
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Cpu_domain_update_list & cpu_domain_update_list() {
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return *unmanaged_singleton<Cpu_domain_update_list>(); }
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void Cpu::Ipi::occurred()
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{
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cpu_domain_update_list().do_each();
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pending = false;
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}
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void Cpu::Ipi::trigger(unsigned const cpu_id)
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{
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if (pending) return;
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pic()->send_ipi(cpu_id);
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pending = true;
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}
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Cpu::Ipi::Ipi(Irq::Pool &p) : Irq(Pic::IPI, p) { }
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/***********************
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** Cpu_domain_update **
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***********************/
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void Cpu_domain_update::_do()
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{
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/* perform domain update locally and get pending bit */
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unsigned const id = Cpu::executing_id();
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if (!_pending[id]) return;
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_domain_update();
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_pending[id] = false;
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/* check wether there are still CPUs pending */
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for (unsigned i = 0; i < NR_OF_CPUS; i++)
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if (_pending[i]) return;
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/* as no CPU is pending anymore, end the domain update */
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cpu_domain_update_list().remove(this);
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_cpu_domain_update_unblocks();
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}
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bool Cpu_domain_update::_do_global(unsigned const domain_id)
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{
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/* perform locally and leave it at that if in uniprocessor mode */
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_domain_id = domain_id;
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_domain_update();
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if (NR_OF_CPUS == 1) return false;
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/* inform other CPUs and block until they are done */
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cpu_domain_update_list().insert_tail(this);
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unsigned const cpu_id = Cpu::executing_id();
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for (unsigned i = 0; i < NR_OF_CPUS; i++) {
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if (i == cpu_id) continue;
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_pending[i] = true;
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cpu_pool()->cpu(i)->trigger_ip_interrupt();
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}
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return true;
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}
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