176 lines
3.5 KiB
C++
176 lines
3.5 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Reto Buerki
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* \date 2015-02-17
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PIC_H_
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#define _PIC_H_
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/* Genode includes */
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#include <util/mmio.h>
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/* core includes */
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#include <board.h>
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namespace Genode
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{
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/**
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* Programmable interrupt controller for core
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*/
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class Pic;
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}
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class Genode::Pic : public Mmio
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{
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private:
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/* Registers */
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struct EOI : Register<0x0b0, 32, true> { };
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struct Svr : Register<0x0f0, 32>
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{
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struct APIC_enable : Bitfield<8, 1> { };
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};
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/*
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* ISR register, see Intel SDM Vol. 3A, section 10.8.4. Each of the 8
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* 32-bit ISR values is followed by 12 bytes of padding.
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*/
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struct Isr : Register_array<0x100, 32, 8 * 4, 32> { };
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class Ioapic : public Mmio
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{
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private:
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uint8_t _irt_count;
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enum {
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/* Number of Redirection Table entries */
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IRTE_COUNT = 0x17,
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IRTE_BIT_POL = 13,
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IRTE_BIT_TRG = 15,
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IRTE_BIT_MASK = 16,
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/* Register selectors */
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IOAPICVER = 0x01,
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IOREDTBL = 0x10,
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};
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/* Create redirection table entry for given IRQ */
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uint64_t create_irt_entry(unsigned irq)
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{
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uint32_t entry = Board::VECTOR_REMAP_BASE + irq;
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if (irq > 15) {
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/* Use level-triggered, high-active mode for non-legacy
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* IRQs */
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entry |= 1 << IRTE_BIT_POL | 1 << IRTE_BIT_TRG;
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}
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return entry;
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}
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public:
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Ioapic() : Mmio(Board::MMIO_IOAPIC_BASE)
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{
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/* Remap all supported IRQs */
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for (unsigned i = 0; i <= IRTE_COUNT; i++) {
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write<Ioregsel>(IOREDTBL + 2 * i);
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write<Iowin>(create_irt_entry(i));
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}
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};
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/* Set/unset mask bit of IRTE for given vector */
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void toggle_mask(unsigned const vector, bool const set)
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{
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if (vector < Board::VECTOR_REMAP_BASE ||
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vector > Board::VECTOR_REMAP_BASE + IRTE_COUNT)
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return;
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write<Ioregsel>(IOREDTBL + (2 * (vector -
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Board::VECTOR_REMAP_BASE)));
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uint32_t val = read<Iowin>();
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if (set) {
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val |= 1 << IRTE_BIT_MASK;
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} else {
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val &= ~(1 << IRTE_BIT_MASK);
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}
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write<Iowin>(val);
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}
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/* Registers */
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struct Ioregsel : Register<0x00, 32> { };
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struct Iowin : Register<0x10, 32> { };
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};
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Ioapic _ioapic;
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/**
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* Determine lowest pending interrupt in ISR register
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*
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* \return index of first ISR bit set starting at index one, zero if no
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* bit is set.
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*/
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inline unsigned get_lowest_bit(void)
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{
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unsigned bit, vec_base = 0;
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for (unsigned i = 0; i < 8 * 4; i += 4) {
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bit = __builtin_ffs(read<Isr>(i));
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if (bit) {
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return vec_base + bit;
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}
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vec_base += 32;
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}
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return 0;
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}
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public:
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enum {
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/*
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* FIXME: dummy ipi value on non-SMP platform, should be removed
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* when SMP is an aspect of CPUs only compiled where
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* necessary
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*/
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IPI = 255,
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NR_OF_IRQ = 256,
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};
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/**
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* Constructor
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*/
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Pic();
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bool take_request(unsigned &irq);
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void finish_request();
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void unmask(unsigned const i, unsigned);
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void mask(unsigned const i);
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/*
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* Dummies
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*/
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void mask() { }
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void init_cpu_local() { }
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bool is_ip_interrupt(unsigned, unsigned) { return false; }
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void trigger_ip_interrupt(unsigned) { }
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};
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namespace Kernel { class Pic : public Genode::Pic { }; }
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#endif /* _PIC_H_ */
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