260 lines
6.1 KiB
C++
260 lines
6.1 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2012-09-11
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__ARM__CPU_H_
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#define _CORE__SPEC__ARM__CPU_H_
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/* Genode includes */
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#include <util/register.h>
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#include <cpu/cpu_state.h>
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#include <hw/spec/arm/cpu.h>
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/* local includes */
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#include <kernel/kernel.h>
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#include <board.h>
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#include <util.h>
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namespace Genode {
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using sizet_arithm_t = Genode::uint64_t;
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struct Arm_cpu;
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}
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struct Genode::Arm_cpu : public Hw::Arm_cpu
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{
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static constexpr addr_t exception_entry = 0xffff0000;
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static constexpr addr_t mtc_size = get_page_size();
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/**
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* Translation table base register 0
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*/
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struct Ttbr0 : Hw::Arm_cpu::Ttbr0
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table)
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{
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access_t v = Ttbr::Ba::masked((addr_t)table);
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Ttbr::Rgn::set(v, CACHEABLE);
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Ttbr::S::set(v, Board::SMP ? 1 : 0);
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if (Board::SMP) Ttbr::Irgn::set(v, CACHEABLE);
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else Ttbr::C::set(v, 1);
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return v;
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}
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};
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struct Dfsr : Hw::Arm_cpu::Dfsr
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{
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struct Wnr : Bitfield<11, 1> { }; /* write not read bit */
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};
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/**
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* Extend basic CPU state by members relevant for 'base-hw' only
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*/
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struct Context : Cpu_state
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{
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Cidr::access_t cidr;
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Ttbr0::access_t ttbr0;
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/**
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* Return base of assigned translation table
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*/
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addr_t translation_table() const {
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return Ttbr::Ba::masked(ttbr0); }
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/**
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* Assign translation-table base 'table'
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*/
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void translation_table(addr_t const table) {
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ttbr0 = Ttbr0::init(table); }
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/**
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* Assign protection domain
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*/
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void protection_domain(Genode::uint8_t const id) { cidr = id; }
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};
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/**
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* This class comprises ARM specific protection domain attributes
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*/
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struct Pd
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{
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Genode::uint8_t asid; /* address space id */
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Pd(Genode::uint8_t id) : asid(id) {}
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};
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/**
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* An usermode execution state
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*/
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struct User_context : Context
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{
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User_context();
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/**
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* Support for kernel calls
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*/
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void user_arg_0(unsigned const arg) { r0 = arg; }
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void user_arg_1(unsigned const arg) { r1 = arg; }
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void user_arg_2(unsigned const arg) { r2 = arg; }
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void user_arg_3(unsigned const arg) { r3 = arg; }
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void user_arg_4(unsigned const arg) { r4 = arg; }
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void user_arg_5(unsigned const arg) { r5 = arg; }
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void user_arg_6(unsigned const arg) { r6 = arg; }
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void user_arg_7(unsigned const arg) { r7 = arg; }
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unsigned user_arg_0() const { return r0; }
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unsigned user_arg_1() const { return r1; }
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unsigned user_arg_2() const { return r2; }
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unsigned user_arg_3() const { return r3; }
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unsigned user_arg_4() const { return r4; }
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unsigned user_arg_5() const { return r5; }
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unsigned user_arg_6() const { return r6; }
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unsigned user_arg_7() const { return r7; }
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/**
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* Initialize thread context
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*
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* \param table physical base of appropriate translation table
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* \param pd_id kernel name of appropriate protection domain
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*/
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void init_thread(addr_t const table, unsigned const pd_id)
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{
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protection_domain(pd_id);
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translation_table(table);
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}
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/**
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* Return if the context is in a page fault due to translation miss
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*
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* \param va holds the virtual fault-address if call returns 1
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* \param w holds wether it's a write fault if call returns 1
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*/
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bool in_fault(addr_t & va, addr_t & w) const
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{
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static constexpr Fsr::access_t section = 5;
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static constexpr Fsr::access_t page = 7;
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switch (cpu_exception) {
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case PREFETCH_ABORT:
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{
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/* check if fault was caused by a translation miss */
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Ifsr::access_t const fs = Fsr::Fs::get(Ifsr::read());
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if (fs != section && fs != page)
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return false;
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/* fetch fault data */
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w = 0;
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va = ip;
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return true;
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}
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case DATA_ABORT:
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{
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/* check if fault was caused by translation miss */
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Dfsr::access_t const fs = Fsr::Fs::get(Dfsr::read());
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if (fs != section && fs != page)
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return false;
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/* fetch fault data */
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Dfsr::access_t const dfsr = Dfsr::read();
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w = Dfsr::Wnr::get(dfsr);
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va = Dfar::read();
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return true;
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}
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default:
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return false;
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};
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}
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};
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/**
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* Returns true if current execution context is running in user mode
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*/
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static bool is_user() { return Psr::M::get(Cpsr::read()) == Psr::M::USR; }
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/**
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* Invalidate all entries of all instruction caches
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*/
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static void invalidate_instr_cache() {
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" :: "r" (0) : ); }
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/**
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* Flush all entries of all data caches
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*/
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static void clean_invalidate_data_cache();
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/**
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* Invalidate all branch predictions
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*/
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static void invalidate_branch_predicts() {
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asm volatile ("mcr p15, 0, r0, c7, c5, 6" ::: "r0"); };
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static constexpr addr_t line_size = 1 << Board::CACHE_LINE_SIZE_LOG2;
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static constexpr addr_t line_align_mask = ~(line_size - 1);
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/**
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* Clean and invalidate data-cache for virtual region
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* 'base' - 'base + size'
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*/
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void clean_invalidate_data_cache_by_virt_region(addr_t base,
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size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Dccimvac::write(base); }
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}
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/**
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* Invalidate instruction-cache for virtual region
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* 'base' - 'base + size'
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*/
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void invalidate_instr_cache_by_virt_region(addr_t base,
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size_t const size)
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{
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addr_t const top = base + size;
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base &= line_align_mask;
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for (; base < top; base += line_size) { Icimvau::write(base); }
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}
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static void wait_for_interrupt();
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/*************
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** Dummies **
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*************/
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void switch_to(User_context&) { }
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bool retry_undefined_instr(Context&) { return false; }
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return 0; }
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id() { return 0; }
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};
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#endif /* _CORE__SPEC__ARM__CPU_H_ */
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