6106e64aac
This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
133 lines
3.1 KiB
C++
133 lines
3.1 KiB
C++
/*
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* \brief Timer driver for core
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* \author Martin stein
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* \date 2011-12-13
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__CORTEX_A9__TIMER_H_
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#define _CORE__SPEC__CORTEX_A9__TIMER_H_
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/* base-hw includes */
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#include <kernel/types.h>
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/* Genode includes */
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#include <util/mmio.h>
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/* core includes */
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#include <board.h>
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namespace Genode { class Timer; }
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/**
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* Timer driver for core
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*/
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class Genode::Timer : public Mmio
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{
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private:
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using time_t = Kernel::time_t;
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enum {
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TICS_PER_MS =
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Board::CORTEX_A9_PRIVATE_TIMER_CLK /
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Board::CORTEX_A9_PRIVATE_TIMER_DIV / 1000
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};
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/**
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* Load value register
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*/
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struct Load : Register<0x0, 32> { };
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/**
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* Counter value register
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*/
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struct Counter : Register<0x4, 32> { };
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/**
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* Timer control register
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*/
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struct Control : Register<0x8, 32>
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{
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struct Timer_enable : Bitfield<0,1> { }; /* enable counting */
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struct Irq_enable : Bitfield<2,1> { }; /* unmask interrupt */
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struct Prescaler : Bitfield<8,8> { };
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};
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/**
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* Timer interrupt status register
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*/
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struct Interrupt_status : Register<0xc, 32>
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{
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struct Event : Bitfield<0,1> { }; /* if counter hit zero */
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};
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public:
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Timer();
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/**
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* Return kernel name of timer interrupt
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*/
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static unsigned interrupt_id(unsigned const) {
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return Board::Cpu_mmio::PRIVATE_TIMER_IRQ; }
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/**
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* Start single timeout run
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*
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* \param tics delay of timer interrupt
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*/
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void start_one_shot(time_t const tics, unsigned const);
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time_t tics_to_us(time_t const tics) const
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{
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/*
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* If we would do the translation with one division and
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* multiplication over the whole argument, we would loose
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* microseconds granularity although the timer frequency would
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* allow for such granularity. Thus, we treat the most significant
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* half and the least significant half of the argument separate.
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* Each half is shifted to the best bit position for the
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* translation, then translated, and then shifted back.
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*/
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static_assert(TICS_PER_MS >= 1000, "Bad TICS_PER_MS value");
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enum {
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TICS_WIDTH = sizeof(time_t) * 8,
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TICS_HALF_WIDTH = TICS_WIDTH / 2,
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TICS_MSB_MASK = ~0UL << TICS_HALF_WIDTH,
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TICS_LSB_MASK = ~0UL >> TICS_HALF_WIDTH,
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TICS_MSB_RSHIFT = 10,
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TICS_LSB_LSHIFT = TICS_HALF_WIDTH - TICS_MSB_RSHIFT,
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};
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time_t const tics_msb = (tics & TICS_MSB_MASK) >> TICS_MSB_RSHIFT;
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time_t const tics_lsb = (tics & TICS_LSB_MASK) << TICS_LSB_LSHIFT;
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time_t const us_msb = ((tics_msb * 1000) / TICS_PER_MS) << TICS_MSB_RSHIFT;
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time_t const us_lsb = ((tics_lsb * 1000) / TICS_PER_MS) >> TICS_LSB_LSHIFT;
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return us_msb | us_lsb;
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}
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time_t us_to_tics(time_t const us) const {
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return (us / 1000) * TICS_PER_MS; }
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/**
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* Return current native timer value
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*/
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time_t value(unsigned const) { return read<Counter>(); }
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time_t max_value() { return (Load::access_t)~0; }
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};
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namespace Kernel { using Genode::Timer; }
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#endif /* _CORE__SPEC__CORTEX_A9__TIMER_H_ */
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