4e97a6511b
* Instead of always re-load page-tables when a thread context is switched only do this when another user PD's thread is the next target, core-threads are always executed within the last PD's page-table set * remove the concept of the mode transition * instead map the exception vector once in bootstrap code into kernel's memory segment * when a new page directory is constructed for a user PD, copy over the top-level kernel segment entries on RISCV and X86, on ARM we use a designated page directory register for the kernel segment * transfer the current CPU id from bootstrap to core/kernel in a register to ease first stack address calculation * align cpu context member of threads and vms, because of x86 constraints regarding the stack-pointer loading * introduce Align_at template for members with alignment constraints * let the x86 hardware do part of the context saving in ISS, by passing the thread context into the TSS before leaving to user-land * use one exception vector for all ARM platforms including Arm_v6 Fix #2091
134 lines
2.7 KiB
Plaintext
134 lines
2.7 KiB
Plaintext
/*
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* \brief Linker script for Genode programs
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* \author Christian Helmuth
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* \date 2006-04-12
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*/
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/*
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* Copyright (C) 2006-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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ENTRY(_start)
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PHDRS
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{
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ro PT_LOAD;
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rw PT_LOAD;
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boot PT_LOAD FLAGS(4);
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}
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SECTIONS
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{
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.text : {
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/* begin of program image (link address) */
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_prog_img_beg = .;
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/* put entry code at the start of the text segment / raw binary */
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KEEP (*(.text.crt0))
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*(.init)
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*(.text .text.* .gnu.linkonce.t.*)
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*(.fini)
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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. = ALIGN(0x08);
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_ctors_start = .;
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KEEP (*(.ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.init_array)) /* list of constructors specific for ARM eabi */
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_ctors_end = .;
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_dtors_start = .;
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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_dtors_end = .;
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} : ro = 0x0
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/* Linux: exception section for uaccess mechanism */
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__ex_table : { *(__ex_table) }
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.eh_frame_hdr : { *(.eh_frame_hdr) }
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. = ALIGN(0x1000);
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.data : {
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/*
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* Leave space for parent capability parameters at start of data
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* section. The protection domain creator is reponsible for storing
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* sane values here.
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*/
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_parent_cap = .;
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_parent_cap_thread_id = .;
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LONG(0xffffffff);
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_parent_cap_local_name = .;
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LONG(0xffffffff);
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LONG(0xffffffff);
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LONG(0xffffffff);
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LONG(0xffffffff);
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LONG(0xffffffff);
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LONG(0xffffffff);
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LONG(0xffffffff);
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/*
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* Platform-specific entry for Fiasco.OC.
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*
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* PIC-code compiled for Fiasco.OC, needs some PIC-compatible
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* way to enter the kernel, the fixed address of the kernel
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* entry code address needs to be found here.
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*/
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__l4sys_invoke_indirect = .;
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LONG(0xeacff000);
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*(.data .gnu.linkonce.d.*)
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/* include all data subsections except those of the boot modules */
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*(EXCLUDE_FILE (*boot_modules.o) .data.*)
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} : rw
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/* exception frames for C++ */
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.eh_frame : {
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__eh_frame_start__ = .;
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KEEP (*(.eh_frame))
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LONG(0)
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} : rw
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.gcc_except_table : {
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KEEP(*(.gcc_except_table))
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KEEP(*(.gcc_except_table.*))
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}
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.dynamic : { *(.dynamic) }
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/* .ARM.exidx is sorted, so has to go in its own output section */
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__exidx_start = .;
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.ARM.exidx : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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}
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__exidx_end = .;
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.ARM.extab : {
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*(.ARM.extab*)
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} : rw
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.bss : {
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_bss_start = ALIGN(4);
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*(.bss .bss.* .gnu.linkonce.b.* COMMON)
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}
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_bss_end = ALIGN(4);
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/* separate location for the binaries of the boot modules */
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.data.boot_modules_binaries : { *(.data.boot_modules_binaries) } : boot
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/* end of program image -- must be after last section */
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_prog_img_end = .;
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/DISCARD/ : {
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*(.note)
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*(.note.ABI-tag)
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*(.comment)
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}
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}
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