6106e64aac
This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
39 lines
941 B
C++
39 lines
941 B
C++
/*
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* \brief Definitions common to all Cortex A9 CPUs
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* \author Stefan Kalkowski
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* \date 2017-02-23
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__ARM__CORTEX_A9_H_
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#define _SRC__LIB__HW__SPEC__ARM__CORTEX_A9_H_
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#include <base/stdint.h>
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namespace Hw { template <Genode::addr_t> struct Cortex_a9_mmio; }
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template <typename Genode::addr_t BASE>
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struct Hw::Cortex_a9_mmio
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{
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enum {
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SCU_MMIO_BASE = BASE,
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IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000,
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IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
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IRQ_CONTROLLER_CPU_BASE = BASE + 0x100,
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IRQ_CONTROLLER_CPU_SIZE = 0x100,
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PRIVATE_TIMER_MMIO_BASE = BASE + 0x600,
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PRIVATE_TIMER_MMIO_SIZE = 0x10,
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PRIVATE_TIMER_IRQ = 29,
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};
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};
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#endif /* _SRC__LIB__HW__SPEC__ARM__CORTEX_A9_H_ */
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