8e13b376b0
This commit addresses several multiprocessing issues in base-hw: * it reworks cross-cpu maintainance work for TLB invalidation by introducing a generic Inter_processor_work and removes the so called Cpu_domain_update * thereby it solves the cross-cpu thread destruction, when the corresponding thread is active on another cpu (fix #3043) * it adds the missing TLB shootdown for x86 (fix #3042) * on ARM it removes the TLB shootdown via IPIs, because this is not needed on the multiprocessing ARM platforms we support * it enables the per-cpu initialization of the kernel's cpu objects, which means those object initialization is executed by the proper cpu * it rollbacks prior decision to make multiprocessing an aspect, but puts back certain 'smp' mechanisms (like cross-cpu lock) into the generic code base for simplicity reasons
49 lines
1.0 KiB
C++
49 lines
1.0 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__IMX53__PIC_H_
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#define _CORE__SPEC__IMX53__PIC_H_
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#include <hw/spec/arm/imx_tzic.h>
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namespace Genode { class Pic; }
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class Genode::Pic : public Hw::Pic
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{
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public:
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enum {
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/*
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* FIXME: dummy ipi value on non-SMP platform, should be removed
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* when SMP is an aspect of CPUs only compiled where necessary
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*/
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IPI = 0,
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};
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/*
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* Trigger interrupt 'i' from software if possible
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*/
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void trigger(unsigned const i) {
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write<Swint>(Swint::Intid::bits(i)); }
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bool secure(unsigned i) {
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return !read<Intsec::Nonsecure>(i); }
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static constexpr bool fast_interrupts() { return true; }
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};
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namespace Kernel { using Pic = Genode::Pic; }
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#endif /* _CORE__SPEC__IMX53__PIC_H_ */
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