651 lines
17 KiB
C++
651 lines
17 KiB
C++
/*
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* \brief Pistachio platform interface implementation
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* \author Christian Helmuth
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* \date 2006-04-11
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*/
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/*
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* Copyright (C) 2006-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* Genode includes */
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#include <base/log.h>
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#include <base/allocator_avl.h>
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#include <base/sleep.h>
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#include <base/capability.h>
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#include <util/misc_math.h>
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/* base-internal includes */
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#include <base/internal/crt0.h>
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#include <base/internal/stack_area.h>
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#include <base/internal/capability_space_tpl.h>
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#include <base/internal/globals.h>
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/* core includes */
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#include <boot_modules.h>
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#include <core_log.h>
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#include <map_local.h>
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#include <platform.h>
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#include <platform_thread.h>
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#include <platform_pd.h>
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#include <util.h>
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#include <kip.h>
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#include <print_l4_thread_id.h>
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/* Pistachio includes */
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namespace Pistachio {
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#include <l4/kip.h>
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#include <l4/sigma0.h>
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#include <l4/space.h>
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#include <l4/bootinfo.h>
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#include <l4/schedule.h>
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}
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using namespace Genode;
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static const bool verbose = true;
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static const bool verbose_core_pf = true;
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/***********************************
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** Core address space management **
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***********************************/
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static Synced_range_allocator<Allocator_avl> &_core_address_ranges()
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{
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static Synced_range_allocator<Allocator_avl> _core_address_ranges(nullptr);
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return _core_address_ranges;
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}
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enum { PAGER_STACK_ELEMENTS = 512 };
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static unsigned long _core_pager_stack[PAGER_STACK_ELEMENTS];
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static inline bool write_fault(Pistachio::L4_Word_t flags) {
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return (flags & 2); }
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static bool wait_for_page_fault(Pistachio::L4_ThreadId_t &from,
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Pistachio::L4_Word_t &pf_addr,
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Pistachio::L4_Word_t &pf_ip,
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Pistachio::L4_Word_t &flags)
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{
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using namespace Pistachio;
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L4_Accept(L4_UntypedWordsAcceptor);
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L4_MsgTag_t res = L4_Wait(&from);
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L4_Msg_t msg;
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enum { EXPECT = 2 };
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if (L4_IpcFailed(res) || (L4_UntypedWords(res)) != EXPECT) {
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error(__func__, ": got ", L4_UntypedWords(res), " words, "
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"expected ", (int)EXPECT);
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return false;
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}
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L4_Store(res, &msg);
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pf_addr = L4_Get(&msg, 0);
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pf_ip = L4_Get(&msg, 1);
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flags = res.X.flags;
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return true;
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}
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static bool reply_and_wait_for_page_fault(Pistachio::L4_ThreadId_t to,
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Pistachio::L4_MapItem_t item,
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Pistachio::L4_ThreadId_t &from,
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Pistachio::L4_Word_t &pf_addr,
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Pistachio::L4_Word_t &pf_ip,
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Pistachio::L4_Word_t &flags)
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{
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using namespace Pistachio;
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L4_Msg_t msg;
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L4_Clear(&msg);
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L4_Append(&msg, item);
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L4_Accept(L4_UntypedWordsAcceptor);
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L4_MsgLoad(&msg);
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L4_MsgTag_t res = L4_ReplyWait(to, &from);
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enum { EXPECT = 2 };
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if (L4_IpcFailed(res) || (L4_UntypedWords(res)) != EXPECT) {
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error(__func__, ": got ", L4_UntypedWords(res), " words, "
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"expected ", (int)EXPECT);
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return wait_for_page_fault(from, pf_addr, pf_ip, flags);
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}
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L4_Store(res, &msg);
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pf_addr = L4_Get(&msg, 0);
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pf_ip = L4_Get(&msg, 1);
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flags = res.X.flags;
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return true;
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}
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/****************
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** Core pager **
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****************/
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static void _core_pager_loop()
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{
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using namespace Pistachio;
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L4_ThreadId_t t;
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L4_Word_t pf_addr, pf_ip;
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L4_Word_t page_size = Genode::get_page_size();
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L4_Word_t flags;
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L4_MapItem_t item;
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bool send_reply = false;
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while (1) {
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if (send_reply)
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reply_and_wait_for_page_fault(t, item, t, pf_addr, pf_ip, flags);
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else
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wait_for_page_fault(t, pf_addr, pf_ip, flags);
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/* XXX Ignore fault messages from non-core tasks */
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/*
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* Check for local echo mapping request. To request a local
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* mappings, a core thread may send an IPC to the core pager with
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* the message word 1 (which normally carries the pf_ip) set to 0.
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* The message word 0 contains a pointer to a map item to be used
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* for the echo reply.
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*/
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if (pf_ip == 0) {
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item = *(L4_MapItem_t *)pf_addr;
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send_reply = true;
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continue;
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}
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log(L4_GlobalId(t));
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/* check for NULL pointer */
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if (pf_addr < page_size) {
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error("possible null pointer ",
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write_fault(flags) ? "WRITE" : "READ/EXEC", " at "
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"address ", Hex(pf_addr), " at EIP ", Hex(pf_ip), " in ", t);
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/* do not unblock faulter */
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break;
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} else if (!_core_address_ranges().valid_addr(pf_addr)) {
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/* page-fault address is not in RAM */
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error(write_fault(flags) ? "WRITE" : "READ", " access outside of RAM "
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"at ", Hex(pf_addr), " IP ", Hex(pf_ip), " by ", t);
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/* do not unblock faulter */
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break;
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} else if (verbose_core_pf) {
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log(__func__, ": pfa=", Hex(pf_addr), " ip=", Hex(pf_ip), " by ", t);
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}
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/* my pf handler is sigma0 - just touch the appropriate page */
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L4_Fpage_t res = L4_Sigma0_GetPage(get_sigma0(),
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L4_Fpage(trunc_page(pf_addr), page_size));
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if (L4_IsNilFpage(res)) {
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panic("Unhandled page fault");
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}
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/* answer pagefault */
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L4_Fpage_t fpage = L4_Fpage(pf_addr, page_size);
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fpage += L4_FullyAccessible;
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item = L4_MapItem(fpage, pf_addr);
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send_reply = true;
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}
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}
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Platform::Sigma0::Sigma0()
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:
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Pager_object(Cpu_session_capability(), Thread_capability(),
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0, Affinity::Location(),
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Session_label(), Cpu_session::Name("sigma0"))
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{
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cap(Capability_space::import(Pistachio::get_sigma0(), Rpc_obj_key()));
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}
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Platform::Sigma0 &Platform::sigma0()
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{
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static Sigma0 _sigma0;
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return _sigma0;
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}
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Platform::Core_pager::Core_pager(Platform_pd &core_pd)
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:
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Platform_thread("core.pager"),
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Pager_object(Cpu_session_capability(), Thread_capability(),
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0, Affinity::Location(),
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Session_label(), Cpu_session::Name(name()))
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{
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Platform_thread::pager(sigma0());
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core_pd.bind_thread(*this);
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cap(Capability_space::import(native_thread_id(), Rpc_obj_key()));
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/* stack begins at the top end of the '_core_pager_stack' array */
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void *sp = (void *)&_core_pager_stack[PAGER_STACK_ELEMENTS - 1];
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start((void *)_core_pager_loop, sp);
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/* pager0 receives pagefaults from me - for NULL pointer detection */
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L4_Set_Pager(native_thread_id());
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}
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Platform::Core_pager &Platform::core_pager()
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{
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static Core_pager _core_pager(core_pd());
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return _core_pager;
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}
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/***********************************
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** Helper for L4 region handling **
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***********************************/
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struct Region
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{
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addr_t start;
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addr_t end;
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Region() : start(0), end(0) { }
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Region(addr_t s, addr_t e) : start(s), end(e) { }
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/**
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* Returns true if the specified range intersects with the region
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*/
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bool intersects(addr_t base, size_t size) const
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{
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return (((base + size) > start) && (base < end));
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}
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void print(Genode::Output &out) const
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{
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size_t const size = end - start;
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Genode::print(out, Hex_range<addr_t>(start, size), " ",
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"size: ", Hex(size, Hex::PREFIX, Hex::PAD));
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}
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};
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/**
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* Add region to allocator
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*/
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static inline void add_region(Region r, Range_allocator &alloc)
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{
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if (r.start >= r.end) {
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error(__func__, ": bad range ", r);
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panic("add_region called with bogus parameters.");
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}
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/* adjust region */
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addr_t start = trunc_page(r.start);
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addr_t end = round_page(r.end);
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alloc.add_range(start, end - start);
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}
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/**
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* Remove region from allocator
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*/
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static inline void remove_region(Region r, Range_allocator &alloc)
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{
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if (r.start >= r.end)
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panic("remove_region called with bogus parameters.");
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/* adjust region */
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addr_t start = trunc_page(r.start);
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addr_t end = round_page(r.end);
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alloc.remove_range(start, end - start);
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}
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static bool intersects_kip_archdep(Pistachio::L4_KernelInterfacePage_t *kip,
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addr_t start, size_t size)
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{
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using namespace Pistachio;
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L4_Word_t num_desc = L4_NumMemoryDescriptors(kip);
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for (L4_Word_t i = 0; i < num_desc; i++) {
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L4_MemoryDesc_t *d = L4_MemoryDesc(kip, i);
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enum { ARCH_DEPENDENT_MEM = 15 };
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if (!L4_IsVirtual(d) && ((L4_Type(d) & 0xF) == ARCH_DEPENDENT_MEM)) {
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if (L4_Low(d) <= start && start <= L4_High(d))
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return true;
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if (L4_Low(d) <= start+size-1 && start+size-1 <= L4_High(d))
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return true;
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if (L4_Low(d) <= start && start+size-1 <= L4_High(d))
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return true;
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}
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}
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return false;
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}
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static void dump_kip_memdesc(Pistachio::L4_KernelInterfacePage_t *kip)
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{
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using namespace Pistachio;
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L4_Word_t num_desc = L4_NumMemoryDescriptors(kip);
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static const char *types[16] =
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{
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"Undefined", "Conventional", "Reserved by kernel",
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"Dedicated", "Shared", "?", "?", "?", "?", "?",
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"?", "?", "?", "?", "Boot loader",
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"Architecture-dependent"
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};
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for (L4_Word_t i = 0; i < num_desc; i++) {
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L4_MemoryDesc_t *d = L4_MemoryDesc(kip, i);
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log("mem ", i, ": ",
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Hex_range<addr_t>(L4_Low(d), L4_High(d) - L4_Low(d) + 1), " "
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"type=", Hex(L4_Type(d)), " (", types[L4_Type(d) & 0xf], ") ",
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L4_IsVirtual(d) ? "Virtual" : "Non-Virtual");
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}
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}
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/**
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* Request any RAM page from Sigma0
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*/
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bool sigma0_req_region(addr_t *addr, unsigned log2size)
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{
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using namespace Pistachio;
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L4_Fpage_t fpage = L4_Sigma0_GetAny(get_sigma0(), log2size,
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L4_CompleteAddressSpace);
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if (L4_IsNilFpage(fpage))
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return false;
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*addr = L4_Address(fpage);
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return true;
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}
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void Platform::_setup_mem_alloc()
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{
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Pistachio::L4_KernelInterfacePage_t *kip = Pistachio::get_kip();
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/*
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* Completely map program image by touching all pages read-only to
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* prevent sigma0 from handing out those page as anonymous memory.
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*/
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volatile const char *beg, *end;
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beg = (const char *)(((unsigned)&_prog_img_beg) & get_page_mask());
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end = (const char *)&_prog_img_end;
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for ( ; beg < end; beg += get_page_size()) (void)(*beg);
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Pistachio::L4_Word_t page_size_mask = Pistachio::L4_PageSizeMask(kip);
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unsigned int size_log2;
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/*
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* Allocate all memory from sigma0 in descending page sizes. Only
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* try page sizes that are hardware supported.
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*/
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for ( size_log2 = 31; page_size_mask != 0; size_log2-- ) {
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unsigned int size = 1 << size_log2;
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/* if this page size is not supported try next */
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if ((page_size_mask & size) == 0)
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continue;
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/* mask out that size bit */
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page_size_mask &= ~size;
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log("Trying to allocate ", size >> 10, "K pages from sigma0.");
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/*
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* Suck out sigma0. The spec says that we get only "conventional
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* memory". Let's hope this is true.
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*/
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bool succ = true;
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unsigned int bytes_got = 0;
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while (succ) {
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addr_t addr;
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Region region;
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succ = sigma0_req_region(&addr, size_log2);
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if (!succ)
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continue;
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/* XXX do not allocate page0 */
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if (addr == 0) {
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// L4_Fpage_t f = L4_FpageLog2(0, pslog2);
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// f += L4_FullyAccessible;
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// L4_Flush(f);
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continue;
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}
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/* exclude phys ram which is unaccessible - 1:1 mappings! */
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if (addr >= _vm_start + _vm_size)
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continue;
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if ((addr + size > _vm_start + _vm_size) || ( addr + size <= addr))
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size = _vm_start + _vm_size - addr;
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region.start = addr; region.end = addr + size;
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if (region.intersects(stack_area_virtual_base(),
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stack_area_virtual_size()) ||
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intersects_kip_archdep(kip, addr, size)) {
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unmap_local(region.start, size >> get_page_size_log2());
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} else {
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add_region(region, _ram_alloc);
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add_region(region, _core_address_ranges());
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}
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remove_region(region, _io_mem_alloc);
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remove_region(region, _region_alloc);
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bytes_got += size;
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}
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log("Got ", bytes_got >> 10, "K in ", size >> 10, "K pieces.");
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}
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}
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void Platform::_setup_irq_alloc() { _irq_alloc.add_range(0, 0x10); }
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void Platform::_setup_preemption()
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{
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/*
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* The roottask has the maximum priority
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*/
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L4_Set_Priority(Pistachio::L4_Myself(),
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Platform_thread::DEFAULT_PRIORITY);
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}
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void Platform::_setup_basics()
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{
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using namespace Pistachio;
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/* store mapping base from received mapping */
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L4_KernelInterfacePage_t *kip = get_kip();
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if (kip->magic != L4_MAGIC)
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panic("we got something but not the KIP");
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if (verbose) {
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log("");
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log("KIP @ ", kip);
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log(" magic: ", Hex(kip->magic, Hex::PREFIX, Hex::PAD));
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log(" version: ", Hex(kip->ApiVersion.raw, Hex::PREFIX, Hex::PAD));
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log(" BootInfo: ", Hex(kip->BootInfo, Hex::PREFIX, Hex::PAD));
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}
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dump_kip_memdesc(kip);
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/* add KIP as ROM module */
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_rom_fs.insert(&_kip_rom);
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L4_Fpage_t bipage = L4_Sigma0_GetPage(get_sigma0(),
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L4_Fpage(kip->BootInfo,
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get_page_size()));
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if (L4_IsNilFpage(bipage))
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panic("Could not map BootInfo.");
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/* done magic */
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/* get UTCB memory */
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Platform_pd::touch_utcb_space();
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/* I/O memory could be the whole user address space */
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_io_mem_alloc.add_range(0, ~0);
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unsigned int kip_size = sizeof(L4_KernelInterfacePage_t);
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_vm_start = 0x0;
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_vm_size = 0x0;
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/*
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* Determine the valid virtual address range by iterating through the
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* memory descriptors provided by the KIP. We expect only one
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* virtual-memory descriptor.
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*/
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for (unsigned i = 0; i < L4_NumMemoryDescriptors(kip); i++) {
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L4_MemoryDesc_t *md = L4_MemoryDesc(kip, i);
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if (!L4_IsVirtual(md)) continue;
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if (_vm_start != 0x0 || _vm_size != 0x0) {
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warning("KIP has multiple virtual-memory descriptors. Taking only the first.");
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break;
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}
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|
/*
|
|
* Exclude the zero page so that we are able to see null-pointer
|
|
* dereference bugs.
|
|
*/
|
|
_vm_start = max((L4_Word_t)0x1000, L4_MemoryDescLow(md));
|
|
_vm_size = L4_MemoryDescHigh(md) - _vm_start + 1;
|
|
|
|
log("KIP reports virtual memory region at ",
|
|
Hex_range<addr_t>(L4_MemoryDescLow(md),
|
|
L4_MemoryDescHigh(md) - L4_MemoryDescLow(md)));
|
|
}
|
|
|
|
/* configure core's virtual memory, exclude KIP, stack area */
|
|
_region_alloc.add_range(_vm_start, _vm_size);
|
|
_region_alloc.remove_range((addr_t)kip, kip_size);
|
|
_region_alloc.remove_range(stack_area_virtual_base(),
|
|
stack_area_virtual_size());
|
|
|
|
/* remove KIP area from region and IO_MEM allocator */
|
|
remove_region(Region((addr_t)kip, (addr_t)kip + kip_size), _region_alloc);
|
|
|
|
/* remove utcb area */
|
|
addr_t utcb_ptr = (addr_t)Platform_pd::_core_utcb_ptr;
|
|
|
|
remove_region(Region(utcb_ptr, utcb_ptr + L4_UtcbAreaSize (kip)), _region_alloc);
|
|
|
|
/* remove core program image memory from region allocator */
|
|
addr_t img_start = (addr_t) &_prog_img_beg;
|
|
addr_t img_end = (addr_t) &_prog_img_end;
|
|
remove_region(Region(img_start, img_end), _region_alloc);
|
|
remove_region(Region(img_start, img_end), _io_mem_alloc);
|
|
|
|
/* image is accessible by core */
|
|
add_region(Region(img_start, img_end), _core_address_ranges());
|
|
}
|
|
|
|
|
|
Platform_pd &Platform::core_pd()
|
|
{
|
|
/* on first call, setup task object for core task */
|
|
static Platform_pd _core_pd(true);
|
|
return _core_pd;
|
|
}
|
|
|
|
|
|
Platform::Platform()
|
|
:
|
|
_ram_alloc(nullptr), _io_mem_alloc(&core_mem_alloc()),
|
|
_io_port_alloc(&core_mem_alloc()), _irq_alloc(&core_mem_alloc()),
|
|
_region_alloc(&core_mem_alloc()),
|
|
_kip_rom((addr_t)Pistachio::get_kip(),
|
|
sizeof(Pistachio::L4_KernelInterfacePage_t), "pistachio_kip")
|
|
{
|
|
/*
|
|
* We must be single-threaded at this stage and so this is safe.
|
|
*/
|
|
static bool initialized = 0;
|
|
if (initialized) panic("Platform constructed twice!");
|
|
initialized = true;
|
|
|
|
_setup_basics();
|
|
_setup_preemption();
|
|
_setup_mem_alloc();
|
|
_setup_io_port_alloc();
|
|
_setup_irq_alloc();
|
|
_init_rom_modules();
|
|
|
|
log(_rom_fs);
|
|
|
|
/*
|
|
* We setup the thread object for thread0 in core task using a
|
|
* special interface that allows us to specify the thread
|
|
* ID. For core, this creates the situation that task_id ==
|
|
* thread_id of first task. But since we do not destroy this
|
|
* task, it should be no problem.
|
|
*/
|
|
static Platform_thread core_thread("core.main");
|
|
|
|
core_thread.set_l4_thread_id(Pistachio::L4_MyGlobalId());
|
|
core_thread.pager(sigma0());
|
|
|
|
core_pd().bind_thread(core_thread);
|
|
|
|
/* core log as ROM module */
|
|
{
|
|
void * phys_ptr = nullptr;
|
|
unsigned const pages = 1;
|
|
size_t const log_size = pages << get_page_size_log2();
|
|
|
|
ram_alloc().alloc_aligned(log_size, &phys_ptr, get_page_size_log2());
|
|
addr_t const phys_addr = reinterpret_cast<addr_t>(phys_ptr);
|
|
|
|
void * const core_local_ptr = phys_ptr;
|
|
addr_t const core_local_addr = phys_addr;
|
|
|
|
/* let one page free after the log buffer */
|
|
region_alloc().remove_range(core_local_addr, log_size + get_page_size());
|
|
|
|
memset(core_local_ptr, 0, log_size);
|
|
|
|
_rom_fs.insert(new (core_mem_alloc()) Rom_module(phys_addr, log_size,
|
|
"core_log"));
|
|
|
|
init_core_log(Core_log_range { core_local_addr, log_size } );
|
|
}
|
|
}
|
|
|
|
|
|
/********************************
|
|
** Generic platform interface **
|
|
********************************/
|
|
|
|
void Platform::wait_for_exit()
|
|
{
|
|
/*
|
|
* On Pistachio, core never exits. So let us sleep forever.
|
|
*/
|
|
sleep_forever();
|
|
}
|
|
|