04516a0d39
This driver component provides support for using consumer NVMe storage devices, i.e. it omits name space managment and will always use the first name space, on Genode. For now it defaults to a reasonable low configuration: - 1 I/O queue (completion/submission tuple) - 128 entries in the I/O queue - 4096 as the only I/O transaction memory page size Fixes #2747.
150 lines
3.3 KiB
C++
150 lines
3.3 KiB
C++
/*
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* \brief NVMe PCIe backend
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* \author Josef Soentgen
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* \date 2018-03-05
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*/
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/*
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* Copyright (C) 2018 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _NVME_PCI_H_
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#define _NVME_PCI_H_
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/* Genode includes */
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#include <irq_session/connection.h>
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#include <platform_device/client.h>
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#include <platform_session/connection.h>
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namespace Nvme {
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using namespace Genode;
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struct Pci;
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}
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struct Nvme::Pci : Platform::Connection,
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Util::Dma_allocator
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{
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struct Missing_controller : Genode::Exception { };
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enum {
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CLASS_MASS_STORAGE = 0x010000u,
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CLASS_MASK = 0xffff00u,
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SUBCLASS_NVME = 0x000800u,
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NVME_DEVICE = CLASS_MASS_STORAGE | SUBCLASS_NVME,
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NVME_PCI = 0x02,
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NVME_BASE_ID = 0,
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};
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enum Pci_config { IRQ = 0x3c, CMD = 0x4, CMD_IO = 0x1,
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CMD_MEMORY = 0x2, CMD_MASTER = 0x4 };
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Platform::Device::Resource _res { };
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Platform::Device_capability _device_cap { };
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Genode::Constructible<Platform::Device_client> _device { };
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Genode::Constructible<Genode::Irq_session_client> _irq { };
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/**
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* Constructor
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*/
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Pci(Genode::Env &env) : Platform::Connection(env)
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{
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upgrade_ram(2*4096u);
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upgrade_caps(8);
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_device_cap = with_upgrade([&] () {
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return next_device(_device_cap,
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NVME_DEVICE, CLASS_MASK);
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});
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if (!_device_cap.valid()) { throw Missing_controller(); }
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_device.construct(_device_cap);
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_res = _device->resource(NVME_BASE_ID);
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uint16_t cmd = _device->config_read(Pci_config::CMD, Platform::Device::ACCESS_16BIT);
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cmd |= 0x2; /* respond to memory space accesses */
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cmd |= 0x4; /* enable bus master */
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_device->config_write(Pci_config::CMD, cmd, Platform::Device::ACCESS_16BIT);
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_irq.construct(_device->irq(0));
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Genode::log("NVMe PCIe controller found (",
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Genode::Hex(_device->vendor_id()), ":",
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Genode::Hex(_device->device_id()), ")");
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}
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/**
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* Return base address of controller MMIO region
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*/
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addr_t base() const { return _res.base(); }
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/**
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* Return size of controller MMIO region
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*/
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size_t size() const { return _res.size(); }
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/**
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* Set interrupt signal handler
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*
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* \parm sigh signal capability
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*/
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void sigh_irq(Genode::Signal_context_capability sigh)
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{
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_irq->sigh(sigh);
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_irq->ack_irq();
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}
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/**
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* Acknowledge interrupt
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*/
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void ack_irq() { _irq->ack_irq(); }
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/*****************************
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** Dma_allocator interface **
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*****************************/
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/**
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* Allocator DMA buffer
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*
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* \param size size of the buffer
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*
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* \return Ram_dataspace_capability
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*/
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Genode::Ram_dataspace_capability alloc(size_t size) override
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{
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size_t donate = size;
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return retry<Out_of_ram>(
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[&] () {
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return retry<Out_of_caps>(
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[&] () { return Pci::Connection::alloc_dma_buffer(size); },
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[&] () { upgrade_caps(2); });
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},
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[&] () {
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upgrade_ram(donate);
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donate = donate * 2 > size ? 4096 : donate * 2;
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});
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}
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/**
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* Free DMA buffer
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*
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* \param cap RAM dataspace capability
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*/
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void free(Genode::Ram_dataspace_capability cap) override
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{
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Pci::Connection::free_dma_buffer(cap);
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}
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};
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#endif /* _NVME_PCI_H_ */
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