abf9557bb5
AVL trees can't be copied with the default copy constructor as the parent pointer of the first item of both of the resulting trees would point to the original tree. Copying an AVL node, however, generally violates the integrity of the corresponding tree. The copy constructor of Avl_tree is used in some places but in those places it can be replaced easily. So, this commit deletes the copy constructor of Avl_node_base which makes Avl_node and Avl_tree non-copyable. Issue #2654
282 lines
6.6 KiB
C++
282 lines
6.6 KiB
C++
/*
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* \brief Kernel backend for virtual machines
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* \author Stefan Kalkowski
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* \date 2015-02-10
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <base/log.h>
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#include <hw/assert.h>
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#include <platform_pd.h>
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#include <kernel/cpu.h>
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#include <kernel/vm.h>
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namespace Kernel
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{
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/**
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* ARM's virtual interrupt controller cpu interface
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*/
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struct Virtual_pic;
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/**
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* ARM's virtual timer counter
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*/
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struct Virtual_timer;
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/**
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* Kernel private virtualization interrupts, delivered to VM/VMMs
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*/
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struct Vm_irq;
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}
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using namespace Kernel;
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extern "C" void kernel();
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extern void * kernel_stack;
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extern "C" void hypervisor_enter_vm(Cpu::Context*);
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struct Host_context {
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addr_t sp;
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addr_t ip;
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Cpu::Ttbr_64bit::access_t ttbr0;
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Cpu::Ttbr_64bit::access_t ttbr1;
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Cpu::Sctlr::access_t sctlr;
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Cpu::Ttbcr::access_t ttbcr;
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Cpu::Mair0::access_t mair0;
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Cpu::Dacr::access_t dacr;
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} vt_host_context;
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struct Kernel::Vm_irq : Kernel::Irq
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{
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Vm_irq(unsigned const irq)
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:
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Kernel::Irq(irq, cpu_pool()->executing_cpu()->irq_pool())
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{ }
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/**
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* A VM interrupt gets injected into the VM scheduled on the current CPU
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*/
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void occurred()
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{
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Cpu_job & job = cpu_pool()->executing_cpu()->scheduled_job();
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Vm *vm = dynamic_cast<Vm*>(&job);
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if (!vm)
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Genode::error("VM timer interrupt while VM is not runnning!");
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else
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vm->inject_irq(_irq_nr);
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}
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};
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struct Kernel::Virtual_pic : Genode::Mmio
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{
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struct Gich_hcr : Register<0x00, 32> { };
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struct Gich_vmcr : Register<0x08, 32> { };
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struct Gich_misr : Register<0x10, 32> { };
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struct Gich_eisr0 : Register<0x20, 32> { };
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struct Gich_elrsr0 : Register<0x30, 32> { };
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struct Gich_apr : Register<0xf0, 32> { };
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template <unsigned SLOT>
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struct Gich_lr : Register<0x100 + SLOT*4, 32> { };
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Vm_irq irq { Board::VT_MAINTAINANCE_IRQ };
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Virtual_pic()
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: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
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static Virtual_pic& pic()
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{
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static Virtual_pic vgic;
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return vgic;
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}
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/**
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* Save the virtual interrupt controller state to VM state
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*/
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static void save (Genode::Vm_state *s)
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{
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s->gic_hcr = pic().read<Gich_hcr >();
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s->gic_misr = pic().read<Gich_misr >();
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s->gic_vmcr = pic().read<Gich_vmcr >();
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s->gic_apr = pic().read<Gich_apr >();
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s->gic_eisr = pic().read<Gich_eisr0 >();
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s->gic_elrsr0 = pic().read<Gich_elrsr0>();
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s->gic_lr[0] = pic().read<Gich_lr<0> >();
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s->gic_lr[1] = pic().read<Gich_lr<1> >();
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s->gic_lr[2] = pic().read<Gich_lr<2> >();
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s->gic_lr[3] = pic().read<Gich_lr<3> >();
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/* disable virtual PIC CPU interface */
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pic().write<Gich_hcr>(0);
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}
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/**
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* Load the virtual interrupt controller state from VM state
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*/
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static void load (Genode::Vm_state *s)
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{
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pic().write<Gich_hcr >(s->gic_hcr );
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pic().write<Gich_misr >(s->gic_misr);
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pic().write<Gich_vmcr >(s->gic_vmcr);
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pic().write<Gich_apr >(s->gic_apr );
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pic().write<Gich_elrsr0>(s->gic_elrsr0);
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pic().write<Gich_lr<0> >(s->gic_lr[0]);
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pic().write<Gich_lr<1> >(s->gic_lr[1]);
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pic().write<Gich_lr<2> >(s->gic_lr[2]);
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pic().write<Gich_lr<3> >(s->gic_lr[3]);
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}
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};
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struct Kernel::Virtual_timer
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{
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Vm_irq irq { Board::VT_TIMER_IRQ };
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/**
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* Return virtual timer object of currently executing cpu
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*
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* FIXME: remove this when re-designing the CPU (issue #1252)
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*/
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static Virtual_timer& timer()
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{
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static Virtual_timer timer[NR_OF_CPUS];
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return timer[Cpu::executing_id()];
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}
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/**
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* Resets the virtual timer, thereby it disables its interrupt
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*/
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static void reset()
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{
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timer().irq.disable();
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asm volatile("mcr p15, 0, %0, c14, c3, 1 \n"
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"mcr p15, 0, %0, c14, c3, 0" :: "r" (0));
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}
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/**
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* Save the virtual timer state to VM state
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*/
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static void save(Genode::Vm_state *s)
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{
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asm volatile("mrc p15, 0, %0, c14, c3, 0 \n"
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"mrc p15, 0, %1, c14, c3, 1" :
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"=r" (s->timer_val), "=r" (s->timer_ctrl));
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}
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/**
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* Load the virtual timer state from VM state
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*/
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static void load(Genode::Vm_state *s)
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{
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if (s->timer_irq) timer().irq.enable();
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asm volatile("mcr p15, 0, %0, c14, c3, 1 \n"
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"mcr p15, 0, %1, c14, c3, 0 \n"
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"mcr p15, 0, %2, c14, c3, 1" ::
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"r" (0),
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"r" (s->timer_val), "r" (s->timer_ctrl));
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}
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};
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using Vmid_allocator = Genode::Bit_allocator<256>;
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static Vmid_allocator &alloc()
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{
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static Vmid_allocator * allocator = nullptr;
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if (!allocator) {
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allocator = unmanaged_singleton<Vmid_allocator>();
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/* reserve VM ID 0 for the hypervisor */
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unsigned id = allocator->alloc();
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assert (id == 0);
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}
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return *allocator;
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}
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Kernel::Vm::Vm(void * const state,
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Kernel::Signal_context * const context,
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void * const table)
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: Cpu_job(Cpu_priority::MIN, 0),
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_id(alloc().alloc()),
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_state((Genode::Vm_state * const)state),
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_context(context),
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_table(table)
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{
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affinity(cpu_pool()->primary_cpu());
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Virtual_pic::pic().irq.enable();
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vt_host_context.sp = _cpu->stack_start();
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vt_host_context.ttbr0 = Cpu::Ttbr0_64bit::read();
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vt_host_context.ttbr1 = Cpu::Ttbr1_64bit::read();
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vt_host_context.sctlr = Cpu::Sctlr::read();
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vt_host_context.ttbcr = Cpu::Ttbcr::read();
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vt_host_context.mair0 = Cpu::Mair0::read();
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vt_host_context.dacr = Cpu::Dacr::read();
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vt_host_context.ip = (addr_t) &kernel;
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}
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Kernel::Vm::~Vm() { alloc().free(_id); }
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void Kernel::Vm::exception(Cpu & cpu)
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{
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Virtual_timer::save(_state);
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switch(_state->cpu_exception) {
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case Genode::Cpu_state::INTERRUPT_REQUEST:
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case Genode::Cpu_state::FAST_INTERRUPT_REQUEST:
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_state->gic_irq = Board::VT_MAINTAINANCE_IRQ;
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_interrupt(cpu.id());
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break;
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default:
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pause();
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_context->submit(1);
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}
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Virtual_pic::save(_state);
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Virtual_timer::reset();
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}
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void Kernel::Vm::proceed(Cpu &)
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{
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/*
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* the following values have to be enforced by the hypervisor
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*/
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_state->vttbr = Cpu::Ttbr_64bit::Ba::masked((Cpu::Ttbr_64bit::access_t)_table);
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Cpu::Ttbr_64bit::Asid::set(_state->vttbr, _id);
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/*
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* use the following report fields not needed for loading the context
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* to transport the HSTR and HCR register descriptions into the assembler
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* path in a dense way
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*/
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_state->hsr = Cpu::Hstr::init();
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_state->hpfar = Cpu::Hcr::init();
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Virtual_pic::load(_state);
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Virtual_timer::load(_state);
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hypervisor_enter_vm(reinterpret_cast<Cpu::Context*>(_state));
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}
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void Vm::inject_irq(unsigned irq)
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{
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_state->gic_irq = irq;
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pause();
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_context->submit(1);
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}
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