ed52d5a211
Instead of holding SPEC-variable dependent files and directories inline within the repository structure, move them into 'spec' subdirectories at the corresponding levels, e.g.: repos/base/include/spec repos/base/mk/spec repos/base/lib/mk/spec repos/base/src/core/spec ... Moreover, this commit removes the 'platform' directories. That term was used in an overloaded sense. All SPEC-relative 'platform' directories are now named 'spec'. Other files, like for instance those related to the kernel/architecture specific startup library, where moved from 'platform' directories to explicit, more meaningful places like e.g.: 'src/lib/startup'. Fix #1673
130 lines
2.7 KiB
C++
130 lines
2.7 KiB
C++
/*
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* \brief Base UART driver for the Xilinx UART PS used on Zynq devices
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* \author Johannes Schlatow
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* \date 2014-12-15
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*/
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/*
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* Copyright (C) 2014-2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__SPEC__XILINX__DRIVERS__UART_BASE_H_
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#define _INCLUDE__SPEC__XILINX__DRIVERS__UART_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Genode { class Xilinx_uartps_base; }
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/**
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* Base driver Xilinx UART PS module
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*/
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class Genode::Xilinx_uartps_base : public Mmio
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{
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protected:
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/**
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* Control register
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*/
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struct Uart_cr : Register<0x00, 32>
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{
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struct Rx_reset : Bitfield<0, 1> { };
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struct Tx_reset : Bitfield<1, 1> { };
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struct Rx_enable : Bitfield<2, 1> { };
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struct Tx_enable : Bitfield<4, 1> { };
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};
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/**
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* Mode register
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*/
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struct Uart_mr : Register<0x04, 32>
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{
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struct Clock_sel : Bitfield<0, 1> { };
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struct Parity : Bitfield<3, 3> { enum { NO_PARITY = 4 }; };
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};
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/**
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* Baudgen register
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*/
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struct Uart_baudgen : Register<0x18, 32>
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{
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struct Clock_div : Bitfield<0, 16> { };
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};
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/**
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* Status register
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*/
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struct Uart_sr : Register<0x2C, 32>
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{
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struct Tx_full : Bitfield<4, 1> { };
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};
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/**
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* FIFO register
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*/
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struct Uart_fifo : Register<0x30, 32>
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{
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struct Data : Bitfield<0, 8> { };
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};
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/**
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* Bauddiv register
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*/
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struct Uart_bauddiv : Register<0x34, 32>
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{
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struct Bdiv : Bitfield<0,8> { };
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};
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public:
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/**
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* Constructor
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*
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* \param base MMIO base address
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* \param clock reference clock
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* \param baud_rate targeted baud rate
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*/
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Xilinx_uartps_base(addr_t const base, unsigned long const clock,
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unsigned long const baud_rate) : Mmio(base)
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{
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/* reset UART */
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Uart_cr::access_t uart_cr = 0;
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Uart_cr::Tx_reset::set(uart_cr, 1);
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Uart_cr::Rx_reset::set(uart_cr, 1);
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write<Uart_cr>(uart_cr);
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/* set baud rate */
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constexpr unsigned div = 4;
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write<Uart_bauddiv::Bdiv>(div);
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write<Uart_baudgen::Clock_div>(clock / baud_rate / (div + 1));
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/* set 8N1 */
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Uart_mr::access_t uart_mr = 0;
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Uart_mr::Parity::set(uart_mr, Uart_mr::Parity::NO_PARITY);
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write<Uart_mr>(uart_mr);
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/* enable */
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uart_cr = 0;
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Uart_cr::Rx_enable::set(uart_cr, 1);
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Uart_cr::Tx_enable::set(uart_cr, 1);
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write<Uart_cr>(uart_cr);
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}
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/**
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* Transmit ASCII char 'c'
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*/
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void put_char(char const c)
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{
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/* wait as long as the transmission buffer is full */
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while (read<Uart_sr::Tx_full>()) ;
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/* transmit character */
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write<Uart_fifo::Data>(c);
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}
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};
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#endif /* _INCLUDE__SPEC__XILINX__DRIVERS__UART_BASE_H_ */
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