157 lines
3.2 KiB
C
157 lines
3.2 KiB
C
/*
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* \brief HDMI subsystem registers
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* \author Norman Feske
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* \date 2012-06-11
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*/
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#ifndef _HDMI_H_
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#define _HDMI_H_
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/* local includes */
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#include <mmio.h>
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struct Hdmi : Mmio
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{
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struct Pwr_ctrl : Register<0x40, 32>
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{
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enum Pll_cmd_type { ALL_OFF = 0,
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BOTH_ON_ALL_CLKS = 2, };
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struct Pll_cmd : Bitfield<2, 2> { };
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struct Pll_status : Bitfield<0, 2> { };
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enum Phy_cmd_type { LDOON = 1,
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TXON = 2 };
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struct Phy_cmd : Bitfield<6, 2> { };
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struct Phy_status : Bitfield<4, 2> { };
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};
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struct Video_cfg : Register<0x50, 32>
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{
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struct Start : Bitfield<31, 1> { };
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struct Packing_mode : Bitfield<8, 3>
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{
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enum { PACK_24B = 1 };
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};
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struct Vsp : Bitfield<7, 1> { };
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struct Hsp : Bitfield<6, 1> { };
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struct Interlacing : Bitfield<3, 1> { };
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struct Tm : Bitfield<0, 2> { };
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};
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struct Video_size : Register<0x60, 32>
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{
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struct X : Bitfield<0, 16> { };
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struct Y : Bitfield<16, 16> { };
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};
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struct Video_timing_h : Register<0x68, 32>
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{
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struct Bp : Bitfield<20, 12> { };
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struct Fp : Bitfield<8, 12> { };
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struct Sw : Bitfield<0, 8> { };
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};
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struct Video_timing_v : Register<0x6c, 32>
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{
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struct Bp : Bitfield<20, 12> { };
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struct Fp : Bitfield<8, 12> { };
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struct Sw : Bitfield<0, 8> { };
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};
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/**
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* \return true on success
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*/
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bool issue_pwr_pll_command(Pwr_ctrl::Pll_cmd_type cmd, Delayer &delayer)
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{
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write<Pwr_ctrl::Pll_cmd>(cmd);
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return wait_for<Pwr_ctrl::Pll_status>(cmd, delayer);
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}
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bool issue_pwr_phy_command(Pwr_ctrl::Phy_cmd_type cmd, Delayer &delayer)
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{
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write<Pwr_ctrl::Phy_cmd>(cmd);
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return wait_for<Pwr_ctrl::Phy_status>(cmd, delayer);
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}
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struct Pll_control : Register<0x200, 32>
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{
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struct Mode : Bitfield<0, 1>
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{
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enum { MANUAL = 0 };
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};
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struct Reset : Bitfield<3, 1> { };
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};
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struct Pll_status : Register<0x204, 32>
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{
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struct Reset_done : Bitfield<0, 1> { };
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struct Pll_locked : Bitfield<1, 1> { };
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};
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bool wait_until_pll_locked(Delayer &delayer)
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{
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return wait_for<Pll_status::Pll_locked>(1, delayer);
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};
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struct Pll_go : Register<0x208, 32>
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{
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struct Go : Bitfield<0, 1> { };
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};
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bool pll_go(Delayer &delayer)
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{
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write<Pll_go::Go>(1);
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/* wait for PLL_GO bit change and the PLL reaching locked state */
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return wait_for<Pll_go::Go>(1, delayer)
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&& wait_until_pll_locked(delayer);
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}
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struct Cfg1 : Register<0x20c, 32>
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{
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struct Regm : Bitfield<9, 12> { };
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struct Regn : Bitfield<1, 8> { };
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};
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struct Cfg2 : Register<0x210, 32>
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{
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struct Highfreq_div_by_2 : Bitfield<12, 1> { };
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struct Refen : Bitfield<13, 1> { };
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struct Clkinen : Bitfield<14, 1> { };
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struct Refsel : Bitfield<21, 2> { };
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struct Freq_divider : Bitfield<1, 3> { };
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};
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struct Cfg4 : Register<0x220, 32>
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{
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struct Regm2 : Bitfield<18, 7> { };
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struct Regmf : Bitfield<0, 18> { };
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};
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bool reset_pll(Delayer &delayer)
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{
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write<Pll_control::Reset>(0);
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return wait_for<Pll_status::Reset_done>(1, delayer);
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};
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struct Txphy_tx_ctrl : Register<0x300, 32>
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{
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struct Freqout : Bitfield<30, 2> { };
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};
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struct Txphy_digital_ctrl : Register<0x304, 32> { };
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Hdmi(Genode::addr_t const mmio_base) : Mmio(mmio_base) { }
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};
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#endif /* _HDMI_H_ */
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