491 lines
15 KiB
ArmAsm
491 lines
15 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland, and secure/non-secure world
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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.include "arm/mode_transition.s"
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.include "macros.s"
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/***************
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** Constants **
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***************/
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/* hardware names of processor modes */
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.set USR_MODE, 16
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.set FIQ_MODE, 17
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.set IRQ_MODE, 18
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.set SVC_MODE, 19
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.set ABT_MODE, 23
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.set UND_MODE, 27
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/* size of local variables */
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.set BUFFER_SIZE, 2 * 4
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/************
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** Macros **
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************/
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/**
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* Determine the base of the client context of the executing processor
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*
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* \param target_reg register that shall receive the base pointer
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* \param buf_reg register that can be polluted by the macro
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*/
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.macro _get_client_context_ptr target_reg, buf_reg
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/* get kernel name of processor */
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_get_processor_id \buf_reg
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/* multiply processor name with pointer size to get offset of pointer */
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mov \target_reg, #CONTEXT_PTR_SIZE
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mul \buf_reg, \buf_reg, \target_reg
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/* get base of the pointer array */
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adr \target_reg, _mt_client_context_ptr
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/* add offset and base to get processor-local pointer */
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add \target_reg, \target_reg, \buf_reg
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ldr \target_reg, [\target_reg]
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.endm
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/**
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* Determine the base of the globally mapped buffer of the executing processor
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*
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* \param target_reg register that shall receive the base pointer
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* \param buf_reg register that can be polluted by the macro
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*/
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.macro _get_buffer_ptr target_reg, buf_reg
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/* get kernel name of processor */
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_get_processor_id \buf_reg
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/* multiply processor name with buffer size to get offset of buffer */
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mov \target_reg, #BUFFER_SIZE
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mul \buf_reg, \buf_reg, \target_reg
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/* get base of the buffer array */
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adr \target_reg, _mt_buffer
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/* add offset and base to get processor-local buffer */
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add \target_reg, \target_reg, \buf_reg
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.endm
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/**
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* Compose a value for the translation-table-base register 0 and apply it
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*
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* \param section_table_reg register that contains targeted section-table base
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*/
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.macro _init_ttbr0 section_table_reg
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/* IRGN bitfield is set to 1 to compose the TTBR0 value */
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orr \section_table_reg, \section_table_reg, #0b1001000
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/* write translation-table-base register 0 */
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mcr p15, 0, \section_table_reg, c2, c0, 0
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/* instruction and data synchronization barrier */
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isb
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dsb
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.endm
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/**
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* Apply a value to the CONTEXTIDR register
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*
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* \param contexidr_reg register that contains the new CONTEXTIDR value
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*/
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.macro _init_contextidr contextidr_reg
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/* write CONTEXTIDR register */
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mcr p15, 0, \contextidr_reg, c13, c0, 1
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/* finish all previous instructions */
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isb
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.endm
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/**
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* Save an interrupted user context and switch to the kernel context
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*
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* \param exception_type kernel name of exception type
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* \param pc_adjust value that gets subtracted from saved user PC
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*/
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.macro _user_to_kernel_pic exception_type, pc_adjust
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/*************************************************************************
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** Still in user protection domain, thus avoid access to kernel memory **
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*************************************************************************/
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/* disable fast interrupts when not in fast-interrupt mode */
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.if \exception_type != FIQ_TYPE
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cpsid f
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.endif
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/*
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* The sp in svc mode still contains the base of the globally mapped
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* buffer of this processor. Hence go to svc mode and buffer user r0 and
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* user r1 to globally mapped memory to be able to pollute r0 and r1.
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*/
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.if \exception_type != RST_TYPE && \exception_type != SVC_TYPE
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cps #SVC_MODE
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.endif
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stm sp, {r0, r1}^
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/* make buffer pointer available to all modes */
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mov r0, sp
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/* switch back to previous privileged mode */
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.if \exception_type == UND_TYPE
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cps #UND_MODE
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.endif
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.if \exception_type == PAB_TYPE
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cps #ABT_MODE
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.endif
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.if \exception_type == DAB_TYPE
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cps #ABT_MODE
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.endif
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.if \exception_type == IRQ_TYPE
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cps #IRQ_MODE
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.endif
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.if \exception_type == FIQ_TYPE
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cps #FIQ_MODE
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.endif
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/* load kernel contextidr and base of the kernel section-table */
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adr sp, _mt_master_context_begin
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add sp, #CONTEXTIDR_OFFSET
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ldm sp, {r1, sp}
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/* switch to kernel protection-domain */
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_init_contextidr r1
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_init_ttbr0 sp
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/*******************************************
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** Now it's save to access kernel memory **
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*******************************************/
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/* get user context-pointer */
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_get_client_context_ptr sp, r1
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/* adjust and save user pc */
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.if \pc_adjust != 0
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sub lr, lr, #\pc_adjust
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.endif
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str lr, [sp, #PC_OFFSET]
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/* move buffer pointer to lr to enable us to save user r0 - r12 via stm */
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mov lr, r0
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/* restore user r0 and user r1 */
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ldm lr, {r0, r1}
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/* save user r0 - r12 */
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stm sp, {r0-r12}^
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/* save user sp and user lr */
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add r0, sp, #SP_OFFSET
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stm r0, {sp, lr}^
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/* get user psr and type of exception that interrupted the user */
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mrs r0, spsr
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mov r1, #\exception_type
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b _common_user_to_kernel_pic
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.endm /* _user_to_kernel_pic */
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/**
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* Save sp, lr and spsr register banks of specified exception mode
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*/
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.macro _save_bank mode
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cps #\mode /* switch to given mode */
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mrs r1, spsr /* store mode-specific spsr */
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stmia r0!, {r1,sp,lr} /* store mode-specific sp and lr */
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.endm /* _save_bank mode */
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/**
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* Switch from an interrupted VM to the kernel context
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*
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* \param exception_type immediate exception type ID
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* \param pc_adjust immediate value that gets subtracted from the
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* vm's PC before it gets saved
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*/
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.macro _vm_to_kernel exception_type, pc_adjust
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ldr sp, _mt_client_context_ptr /* load context pointer */
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stmia sp, {r0-lr}^ /* save user regs r0-r12,sp,lr */
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add r0, sp, #15*4
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.if \pc_adjust != 0 /* adjust pc if necessary */
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sub lr, lr, #\pc_adjust
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.endif
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stmia r0!, {lr} /* save pc */
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mrs r1, spsr /* spsr to r0 */
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mov r2, #\exception_type /* exception reason to r1 */
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stmia r0!, {r1-r2} /* save spsr, and exception reason */
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mrc p15, 0, r3, c6, c0, 0 /* move DFAR to r3 */
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mrc p15, 0, r4, c2, c0, 0 /* move TTBR0 to r4 */
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mrc p15, 0, r5, c2, c0, 1 /* move TTBR1 to r5 */
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mrc p15, 0, r6, c2, c0, 2 /* move TTBRC to r6 */
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mov r1, #0
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mcr p15, 0, r1, c1, c1, 0 /* disable non-secure bit */
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_save_bank 27 /* save undefined banks */
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_save_bank 19 /* save supervisor banks */
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_save_bank 23 /* save abort banks */
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_save_bank 18 /* save irq banks */
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_save_bank 17 /* save fiq banks */
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stmia r0!, {r8-r12} /* save fiq r8-r12 */
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stmia r0!, {r3-r6} /* save MMU registers */
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b _common_client_to_kernel_pic
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.endm /* _vm_to_kernel */
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/**
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* Restore sp, lr and spsr register banks of specified exception mode
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*/
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.macro _restore_bank mode
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cps #\mode /* switch to given mode */
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ldmia r0!, {r1,sp,lr} /* load mode-specific sp, lr, and spsr into r1 */
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msr spsr_cxfs, r1 /* load mode-specific spsr */
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.endm
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/**
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* Switch from kernel context to a VM
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*/
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.macro _kernel_to_vm
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ldr r0, _mt_client_context_ptr /* get vm context pointer */
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add r0, r0, #18*4 /* add offset of banked modes */
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_restore_bank 27 /* load undefined banks */
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_restore_bank 19 /* load supervisor banks */
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_restore_bank 23 /* load abort banks */
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_restore_bank 18 /* load irq banks */
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_restore_bank 17 /* load fiq banks */
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ldmia r0!, {r8 - r12} /* load fiq r8-r12 */
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cps #22 /* switch to monitor mode */
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ldr sp, _mt_client_context_ptr /* get vm context pointer */
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ldmia sp, {r0-lr}^ /* load user r0-r12,sp,lr */
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ldr lr, [sp, #16*4] /* load vm's cpsr to lr */
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msr spsr_cxfs, lr /* save cpsr to be load when switching */
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mov lr, #13
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mcr p15, 0, lr, c1, c1, 0 /* enable EA, FIQ, and NS bit in SCTRL */
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ldr lr, [sp, #15*4] /* load vm's ip */
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subs pc, lr, #0
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.endm /* _kernel_to_vm */
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/**********************************
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** Linked into the text section **
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**********************************/
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.section .text
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/*
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* Page aligned base of mode transition code.
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*
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* This position independent code switches between a kernel context and a
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* user context and thereby between their address spaces. Due to the latter
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* it must be mapped executable to the same region in every address space.
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* To enable such switching, the kernel context must be stored within this
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* region, thus one should map it solely accessable for privileged modes.
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*/
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.p2align MIN_PAGE_SIZE_LOG2
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.global _mt_begin
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_mt_begin:
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/*
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* On user exceptions the CPU has to jump to one of the following
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* seven entry vectors to switch to a kernel context.
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*/
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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/***********************
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** Exception entries **
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***********************/
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b _rst_entry /* 0x00: reset */
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b _und_entry /* 0x04: undefined instruction */
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b _svc_entry /* 0x08: supervisor call */
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b _pab_entry /* 0x0c: prefetch abort */
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b _dab_entry /* 0x10: data abort */
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nop /* 0x14: reserved */
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b _irq_entry /* 0x18: interrupt request */
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/******************************************************
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** Entry for fast interrupt requests at offset 0x1c **
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******************************************************/
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/* load the saved PSR of the the previous mode */
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mrs r8, spsr
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/* get the M bitfield from the read PSR value */
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and r9, r8, #0b11111
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/* skip following instructions if previous mode was user mode */
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cmp r9, #USR_MODE
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beq 1f
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/*
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* If we reach this point, the previous mode was not the user
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* mode, meaning an exception entry has been preempted by this
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* fast interrupt before it could disable fast interrupts.
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*/
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/* disable fast interrupts in PSR value of previous mode */
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orr r8, #0b1000000
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/* apply PSR of previous mode */
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msr spsr, r8
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/*
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* Resume excecution of previous exception entry leaving the fast
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* interrupt unhandled till fast interrupts get enabled again.
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*/
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subs pc, lr, #4
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/* switch to kernel to handle the fast interrupt */
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1:
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_user_to_kernel_pic FIQ_TYPE, FIQ_PC_ADJUST
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/***************************************************************
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** Code that switches from a non-FIQ exception to the kernel **
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***************************************************************/
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_rst_entry: _user_to_kernel_pic RST_TYPE, RST_PC_ADJUST
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_und_entry: _user_to_kernel_pic UND_TYPE, UND_PC_ADJUST
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_svc_entry: _user_to_kernel_pic SVC_TYPE, SVC_PC_ADJUST
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_pab_entry: _user_to_kernel_pic PAB_TYPE, PAB_PC_ADJUST
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_dab_entry: _user_to_kernel_pic DAB_TYPE, DAB_PC_ADJUST
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_irq_entry: _user_to_kernel_pic IRQ_TYPE, IRQ_PC_ADJUST
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/**************************************************************
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** Kernel-entry code that is common for all user exceptions **
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**************************************************************/
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_common_user_to_kernel_pic:
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/* save user psr and type of exception that interrupted the user */
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add sp, sp, #PSR_OFFSET
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stm sp, {r0, r1}
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/*********************************************************
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** Kernel-entry code that is common for all exceptions **
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*********************************************************/
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_common_client_to_kernel_pic:
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/*
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* Switch to supervisor mode to circumvent incorrect behavior of
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* kernel high-level code in fast interrupt mode and to ensure that
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* we're in svc mode at kernel exit. The latter is because kernel
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* exit stores a buffer pointer into its banked sp that is also
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* needed by the subsequent kernel entry.
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*/
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cps #SVC_MODE
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/* get base of the kernel-stacks area and the kernel-stack size */
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adr r0, _mt_master_context_begin
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add r1, r0, #R12_OFFSET
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ldm r1, {r2, r3}
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/* determine top of the kernel stack of this processor and apply it as SP */
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_init_kernel_sp r3, r2
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/* apply kernel lr and kernel pc */
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add r1, r0, #LR_OFFSET
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ldm r1, {lr, pc}
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_mt_local_variables
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/****************************************************************
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** Code that switches from a kernel context to a user context **
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****************************************************************/
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.p2align 2
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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/* get user context and globally mapped buffer of this processor */
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_get_client_context_ptr lr, r0
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_get_buffer_ptr sp, r0
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/* buffer user pc and base of user section-table globally mapped */
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ldr r0, [lr, #PC_OFFSET]
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ldr r1, [lr, #SECTION_TABLE_OFFSET]
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stm sp, {r0, r1}
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/* buffer user psr in spsr */
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ldr r0, [lr, #PSR_OFFSET]
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msr spsr, r0
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/* setup banked user sp and banked user lr */
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add r0, lr, #SP_OFFSET
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ldm r0, {sp, lr}^
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/* setup user r0 to r12 */
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ldm lr, {r0-r12}^
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/* load user contextidr */
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ldr lr, [lr, #CONTEXTIDR_OFFSET]
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/********************************************************
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** From now on, until we leave kernel mode, we must **
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** avoid access to memory that is not mapped globally **
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********************************************************/
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/* switch to user protection-domain */
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_init_contextidr lr
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ldr lr, [sp, #4]
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_init_ttbr0 lr
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/* apply user pc which implies application of spsr as user psr */
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ldm sp, {pc}^
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/*
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* On vm exceptions the CPU has to jump to one of the following
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* 7 entry vectors to switch to a kernel context.
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*/
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.p2align 4
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.global _mon_kernel_entry
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_mon_kernel_entry:
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b _mon_rst_entry /* reset */
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b _mon_und_entry /* undefined instruction */
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b _mon_svc_entry /* supervisor call */
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b _mon_pab_entry /* prefetch abort */
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b _mon_dab_entry /* data abort */
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nop /* reserved */
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b _mon_irq_entry /* interrupt request */
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_vm_to_kernel FIQ_TYPE, 4 /* fast interrupt request */
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/* PICs that switch from a vm exception to the kernel */
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_mon_rst_entry: _vm_to_kernel RST_TYPE, 0
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_mon_und_entry: _vm_to_kernel UND_TYPE, 4
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_mon_svc_entry: _vm_to_kernel SVC_TYPE, 0
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_mon_pab_entry: _vm_to_kernel PAB_TYPE, 4
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_mon_dab_entry: _vm_to_kernel DAB_TYPE, 8
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_mon_irq_entry: _vm_to_kernel IRQ_TYPE, 4
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/* kernel must jump to this point to switch to a vm */
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.p2align 2
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.global _mt_vm_entry_pic
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_mt_vm_entry_pic:
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_kernel_to_vm
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/* end of the mode transition code */
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.global _mt_end
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_mt_end:
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