620 lines
15 KiB
C++
620 lines
15 KiB
C++
/*
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* \brief VirtualBox page manager (PGM)
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* \author Norman Feske
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* \date 2013-08-20
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is distributed under the terms of the GNU General Public License
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* version 2.
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*/
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/* Genode includes */
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#include <base/printf.h>
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#include <util/string.h>
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#include <vmm/printf.h>
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/* VirtualBox includes */
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#include "PGMInternal.h" /* enable access to pgm.s.* */
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#include <VBox/vmm/mm.h>
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#include <VBox/vmm/vm.h>
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#include <VBox/vmm/pgm.h>
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#include <VBox/vmm/rem.h>
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#include <iprt/err.h>
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/* local includes */
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#include "util.h"
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#include "vmm_memory.h"
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#include "guest_memory.h"
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using Genode::Ram_session;
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using Genode::Rm_session;
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Vmm_memory *vmm_memory()
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{
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static Vmm_memory inst(*Genode::env()->ram_session());
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return &inst;
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}
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Guest_memory *guest_memory()
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{
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static Guest_memory inst;
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return &inst;
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}
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int PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
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RTGCPHYS cb, const void *pvBinary, uint32_t cbBinary,
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uint32_t fFlags, const char *pszDesc)
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{
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PLOG("PGMR3PhysRomRegister: GCPhys=0x%lx cb=0x%zx pvBinary=0x%p",
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(long)GCPhys, (size_t)cb, pvBinary);
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try {
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guest_memory()->add_rom_mapping(GCPhys, cb, pvBinary, pDevIns);
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guest_memory()->dump();
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/*
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* XXX Try to understand the fShadowed condition
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* (see pgmR3PhysRomRegister)
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*/
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REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
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} catch (Guest_memory::Region_conflict) {
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return VERR_PGM_MAPPING_CONFLICT; }
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return VINF_SUCCESS;
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}
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int PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
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{
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void *pv = guest_memory()->lookup(GCPhys, cbWrite);
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if (pv) {
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memcpy(pv, pvBuf, cbWrite);
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return VINF_SUCCESS;
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}
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PFNPGMR3PHYSHANDLER pfnHandlerR3 = 0;
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void *pvUserR3 = 0;
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pv = vmm_memory()->lookup(GCPhys, cbWrite, &pfnHandlerR3, &pvUserR3);
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if (!pv || !pfnHandlerR3 || !pvUserR3) {
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PERR("PGMPhysWrite skipped: GCPhys=0x%lx pvBuf=0x%p cbWrite=0x%zx",
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GCPhys, pvBuf, cbWrite);
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return VERR_GENERAL_FAILURE;
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}
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int rc = pfnHandlerR3(pVM, GCPhys, 0, 0, cbWrite, PGMACCESSTYPE_WRITE,
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pvUserR3);
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if (rc == VINF_PGM_HANDLER_DO_DEFAULT) {
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memcpy(pv, pvBuf, cbWrite);
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return VINF_SUCCESS;
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}
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PERR("unexpected %s return code %d", __FUNCTION__, rc);
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return VERR_GENERAL_FAILURE;
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}
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int PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf,
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size_t cbWrite, const char *pszWho)
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{
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// PDBG("GCPhys=0x%llx pvBuf=0x%p cbWrite=0x%zx - '%s'",
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// GCPhys, pvBuf, cbWrite, pszWho);
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return PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite);
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}
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int PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
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{
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void *pv = guest_memory()->lookup(GCPhys, cbRead);
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// PLOG("PGMPhysRead: GCPhys=0x%x pvBuf=0x%p cbRead=0x%zx pv=%p",
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// GCPhys, pvBuf, cbRead, pv);
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if (pv) {
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memcpy(pvBuf, pv, cbRead);
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return VINF_SUCCESS;
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}
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PFNPGMR3PHYSHANDLER pfnHandlerR3 = 0;
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void *pvUserR3 = 0;
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pv = vmm_memory()->lookup(GCPhys, cbRead, &pfnHandlerR3, &pvUserR3);
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if (!pv || !pfnHandlerR3 || !pvUserR3) {
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PERR("PGMPhysRead skipped: GCPhys=0x%lx pvBuf=0x%p cbRead=0x%zx",
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GCPhys, pvBuf, cbRead);
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return VERR_GENERAL_FAILURE;
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}
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memcpy(pvBuf, pv, cbRead);
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return VINF_SUCCESS;
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}
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int PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
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{
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void *pv = guest_memory()->lookup(GCPhys, cbRead);
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// PLOG("PGMPhysReadExternal: GCPhys=0x%x pvBuf=0x%p cbRead=0x%zx pv=%p",
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// GCPhys, pvBuf, cbRead, pv);
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return PGMPhysRead(pVM, GCPhys, pvBuf, cbRead);
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}
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int PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion,
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RTGCPHYS cb, uint32_t fFlags, void **ppv, const char
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*pszDesc)
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{
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*ppv = vmm_memory()->alloc((size_t)cb, pDevIns, iRegion);
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PLOG("PGMR3PhysMMIO2Register: pszDesc=%s iRegion=%u cb=0x%zx -> 0x%p",
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pszDesc, iRegion, (size_t)cb, *ppv);
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return VINF_SUCCESS;
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}
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int PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion,
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RTGCPHYS GCPhys)
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{
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size_t cb = vmm_memory()->map_to_vm(pDevIns, iRegion, GCPhys);
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if (cb == 0) {
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PERR("PGMR3PhysMMIO2Map: lookup for pDevIns=%p iRegion=%u failed\n",
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pDevIns, iRegion);
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for (;;);
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}
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PLOG("PGMR3PhysMMIO2Map: pDevIns=%p iRegion=%u cb=0x%zx GCPhys=0x%lx\n",
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pDevIns, iRegion, cb, (long)GCPhys);
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REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
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return VINF_SUCCESS;
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}
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int PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion,
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RTGCPHYS GCPhys)
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{
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PDBG("called %x %x", GCPhys, iRegion);
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vmm_memory()->map_to_vm(pDevIns, iRegion, 0);
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return VINF_SUCCESS;
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}
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bool PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
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{
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bool res = vmm_memory()->lookup(GCPhys, 1);
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PDBG("called %x %u", GCPhys, res);
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return res;
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}
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int PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType,
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RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
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PFNPGMR3PHYSHANDLER pfnHandlerR3,
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void *pvUserR3, const char *pszModR0,
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const char *pszHandlerR0, RTR0PTR pvUserR0,
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const char *pszModRC,
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const char *pszHandlerRC,
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RTRCPTR pvUserRC, const char *pszDesc)
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{
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PLOG("PGMR3HandlerPhysicalRegister: pszDesc=%s %u GCPhys=0x%lx GCPhysLast=0x%lx r3=0x%p\n",
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pszDesc, enmType, (long)GCPhys, (long)GCPhysLast, (void *)pfnHandlerR3);
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REMR3NotifyHandlerPhysicalRegister(pVM, enmType, GCPhys, GCPhysLast - GCPhys + 1, !!pfnHandlerR3);
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vmm_memory()->add_handler(GCPhys, GCPhysLast - GCPhys + 1, pfnHandlerR3,
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pvUserR3);
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return VINF_SUCCESS;
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}
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int PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys)
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{
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PDBG("called %x", GCPhys);
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/*
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for(;;);
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pgmHandlerPhysicalResetRamFlags(pVM, pCur);
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REMR3NotifyHandlerPhysicalDeregister(pVM, pCur->enmType, GCPhysStart, GCPhysLast - GCPhysStart + 1, !!pCur->pfnHandlerR3, fRestoreAsRAM);
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*/
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vmm_memory()->add_handler(GCPhys, GCPhys + 1, 0, 0);
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return VINF_SUCCESS;
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return VERR_PGM_HANDLER_NOT_FOUND;
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}
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int PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
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const char *pszDesc)
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{
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PLOG("PGMR3PhysRegisterRam: GCPhys=0x%lx, cb=0x%zx, pszDesc=%s",
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(long)GCPhys, (size_t)cb, pszDesc);
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try {
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/*
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* XXX Is this function the right place for the allocation?
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* The lack of allocation-related VERR_PGM_ error codes suggests
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* so.
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*/
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void *pv = vmm_memory()->alloc_ram((size_t)cb);
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guest_memory()->add_ram_mapping(GCPhys, cb, pv);
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guest_memory()->dump();
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REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
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}
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catch (Guest_memory::Region_conflict) {
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return VERR_PGM_MAPPING_CONFLICT; }
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catch (Ram_session::Alloc_failed) {
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return VERR_PGM_MAPPING_CONFLICT; /* XXX use a better error code? */ }
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catch (Rm_session::Attach_failed) {
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return VERR_PGM_MAPPING_CONFLICT; /* XXX use a better error code? */ }
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return VINF_SUCCESS;
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}
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int PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
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{
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PLOG("PGMMapSetPage: GCPtr=0x%lx cb=0x%lx, flags=0x%lx",
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(long)GCPtr, (long)cb, (long)fFlags);
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return VINF_SUCCESS;
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}
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RTHCPHYS PGMGetHyperCR3(PVMCPU pVCpu)
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{
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// PDBG("%s %lx", __func__, CPUMGetHyperCR3(pVCpu));
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return 1;
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}
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int PGMR3Init(PVM pVM)
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{
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/*
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* Satisfy assertion in VMMR3Init. Normally called via:
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*
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* PGMR3Init -> pgmR3InitPaging -> pgmR3ModeDataInit -> InitData -> MapCR3
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*/
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for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++) {
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PVMCPU pVCpu = &pVM->aCpus[idCpu];
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CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
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pVCpu->pgm.s.fA20Enabled = true;
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pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
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}
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return VINF_SUCCESS;
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}
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int PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
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{
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size_t const size = 1;
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void *pv = guest_memory()->lookup(GCPhys, size);
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if (pv) {
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*ppv = pv;
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return VINF_SUCCESS;
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}
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PFNPGMR3PHYSHANDLER pfnHandlerR3 = 0;
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void *pvUserR3 = 0;
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pv = vmm_memory()->lookup(GCPhys, size, &pfnHandlerR3, &pvUserR3);
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if (!pv) {
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PERR("%s: lookup for GCPhys=0x%p failed", __func__, GCPhys);
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return VERR_PGM_PHYS_TLB_UNASSIGNED;
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}
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/* pv valid - check handlers next */
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if (!pfnHandlerR3 && !pvUserR3) {
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*ppv = pv;
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return VINF_SUCCESS;
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}
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PERR("%s: denied access - handlers set - GCPhys=0x%p", __func__, GCPhys);
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return VERR_PGM_PHYS_TLB_CATCH_ALL;
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}
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void PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
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{
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if (!pVCpu->pgm.s.fA20Enabled != fEnable) {
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pVCpu->pgm.s.fA20Enabled = fEnable;
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REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
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}
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return;
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}
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bool PGMPhysIsA20Enabled(PVMCPU pVCpu)
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{
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return pVCpu->pgm.s.fA20Enabled;
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}
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void PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t value)
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{
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void *pv = guest_memory()->lookup(GCPhys, sizeof(value));
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if (!pv) {
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PDBG("invalid write attempt");
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return;
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}
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*reinterpret_cast<uint8_t *>(pv) = value;
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}
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void PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t value)
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{
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void *pv = guest_memory()->lookup(GCPhys, sizeof(value));
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if (!pv) {
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PDBG("invalid write attempt");
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return;
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}
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*reinterpret_cast<uint16_t *>(pv) = value;
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}
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void PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t value)
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{
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void *pv = guest_memory()->lookup(GCPhys, sizeof(value));
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if (!pv) {
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PDBG("invalid write attempt");
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return;
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}
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*reinterpret_cast<uint32_t *>(pv) = value;
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}
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uint32_t PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys)
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{
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void *pv = guest_memory()->lookup(GCPhys, 4);
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if (!pv) {
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PDBG("invalid read attempt");
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return 0;
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}
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return *reinterpret_cast<uint32_t *>(pv);
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}
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int PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv,
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PPGMPAGEMAPLOCK pLock)
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{
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PDBG("not implemented");
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while (1) {}
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return VINF_SUCCESS;
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}
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int PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode) {
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// Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
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// PDBG("not implemented %x %x", pVCpu->pgm.s.enmShadowMode, PGMMODE_EPT);
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pVCpu->pgm.s.enmGuestMode = enmGuestMode;
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HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
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return VINF_SUCCESS;
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}
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int PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
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{
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PGMMODE enmGuestMode;
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VMCPU_ASSERT_EMT(pVCpu);
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/*
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* Calc the new guest mode.
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*/
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if (!(cr0 & X86_CR0_PE))
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enmGuestMode = PGMMODE_REAL;
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else if (!(cr0 & X86_CR0_PG))
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enmGuestMode = PGMMODE_PROTECTED;
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else if (!(cr4 & X86_CR4_PAE))
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{
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bool const fPse = !!(cr4 & X86_CR4_PSE);
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if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
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Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
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pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
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enmGuestMode = PGMMODE_32_BIT;
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}
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else if (!(efer & MSR_K6_EFER_LME))
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{
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if (!(efer & MSR_K6_EFER_NXE))
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enmGuestMode = PGMMODE_PAE;
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else
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enmGuestMode = PGMMODE_PAE_NX;
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}
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else
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{
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if (!(efer & MSR_K6_EFER_NXE))
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enmGuestMode = PGMMODE_AMD64;
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else
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enmGuestMode = PGMMODE_AMD64_NX;
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}
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/*
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* Did it change?
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*/
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if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
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return VINF_SUCCESS;
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/* Flush the TLB */
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// PGM_INVL_VCPU_TLBS(pVCpu);
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VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
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// PDBG("not implemented %x %x before", enmGuestMode, pVCpu->pgm.s.enmGuestMode);
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int rc = PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
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// PDBG("not implemented %x %x out %p", enmGuestMode, pVCpu->pgm.s.enmGuestMode, __builtin_return_address(0));
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// return VINF_PGM_CHANGE_MODE;
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return rc;
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}
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/*
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* Copied from src/VBox/VMM/VMMAll/PGMAll.cpp
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*/
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PGMMODE PGMGetGuestMode(PVMCPU pVCpu) { return pVCpu->pgm.s.enmGuestMode; }
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VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
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{
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switch (enmMode)
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{
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case PGMMODE_REAL: return "Real";
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case PGMMODE_PROTECTED: return "Protected";
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case PGMMODE_32_BIT: return "32-bit";
|
|
case PGMMODE_PAE: return "PAE";
|
|
case PGMMODE_PAE_NX: return "PAE+NX";
|
|
case PGMMODE_AMD64: return "AMD64";
|
|
case PGMMODE_AMD64_NX: return "AMD64+NX";
|
|
case PGMMODE_NESTED: return "Nested";
|
|
case PGMMODE_EPT: return "EPT";
|
|
default: return "unknown mode value";
|
|
}
|
|
}
|
|
|
|
|
|
int PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
|
|
{
|
|
void *pv = guest_memory()->lookup(GCPhys, 0x1000);
|
|
|
|
if (!pv) {
|
|
PDBG("unknown address pv=%p ppv=%p GCPhys=%llx", pv, ppv, GCPhys);
|
|
|
|
guest_memory()->dump();
|
|
|
|
return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
|
|
}
|
|
|
|
*ppv = pv;
|
|
|
|
PVMCPU pVCpu = VMMGetCpu(pVM);
|
|
|
|
return VINF_SUCCESS;
|
|
}
|
|
|
|
|
|
int PGMHandlerPhysicalReset(PVM, RTGCPHYS GCPhys)
|
|
{
|
|
if (!vmm_memory()->unmap_from_vm(GCPhys))
|
|
PWRN("%s: unbacked region - GCPhys %lx", __func__, GCPhys);
|
|
|
|
return VINF_SUCCESS;
|
|
}
|
|
|
|
|
|
extern "C" int MMIO2_MAPPED_SYNC(PVM pVM, RTGCPHYS GCPhys, size_t cbWrite,
|
|
void **ppv)
|
|
{
|
|
/* DON'T USE normal printf in this function - corrupts unsaved UTCB !!! */
|
|
|
|
PFNPGMR3PHYSHANDLER pfnHandlerR3 = 0;
|
|
void *pvUserR3 = 0;
|
|
|
|
void * pv = vmm_memory()->lookup(GCPhys, cbWrite, &pfnHandlerR3, &pvUserR3);
|
|
|
|
if (!pv)
|
|
return VERR_PGM_PHYS_TLB_UNASSIGNED;
|
|
|
|
if (!pfnHandlerR3 && !pvUserR3) {
|
|
*ppv = pv;
|
|
/* you may map it */
|
|
return VINF_SUCCESS;
|
|
}
|
|
|
|
if (pfnHandlerR3 && pvUserR3) {
|
|
int rc = pfnHandlerR3(pVM, GCPhys, 0, 0, cbWrite, PGMACCESSTYPE_WRITE,
|
|
pvUserR3);
|
|
|
|
if (rc == VINF_PGM_HANDLER_DO_DEFAULT) {
|
|
*ppv = pv;
|
|
/* you may map it */
|
|
return VINF_SUCCESS;
|
|
}
|
|
|
|
Vmm::printf("%s: GCPhys=0x%lx failed - unexpected rc=%d\n",
|
|
__func__, GCPhys, rc);
|
|
return rc;
|
|
}
|
|
|
|
Vmm::printf("%s: GCPhys=0x%lx failed - unexpected state \n",
|
|
__func__, GCPhys);
|
|
return VERR_GENERAL_FAILURE;
|
|
}
|
|
|
|
|
|
void PGMR3Reset(PVM pVM)
|
|
{
|
|
VM_ASSERT_EMT(pVM);
|
|
|
|
for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
|
{
|
|
int rc = PGMR3ChangeMode(pVM, &pVM->aCpus[i], PGMMODE_REAL);
|
|
AssertRC(rc);
|
|
}
|
|
|
|
for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
|
{
|
|
PVMCPU pVCpu = &pVM->aCpus[i];
|
|
|
|
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
|
|
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
|
|
|
|
if (!pVCpu->pgm.s.fA20Enabled)
|
|
{
|
|
pVCpu->pgm.s.fA20Enabled = true;
|
|
pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
|
|
#ifdef PGM_WITH_A20
|
|
pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
|
|
VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
|
|
HWACCMFlushTLB(pVCpu);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
PERR("clearing ram and rom areas missing !!!!!!!");
|
|
}
|
|
|
|
|
|
int PGMR3MappingsSize(PVM pVM, uint32_t *pcb)
|
|
{
|
|
PINF("%s - not implemented - %p", __func__, __builtin_return_address(0));
|
|
|
|
*pcb = 0;
|
|
|
|
return 0;
|
|
}
|