734 lines
20 KiB
C++
734 lines
20 KiB
C++
/*
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* \brief Genode/Nova specific VirtualBox SUPLib supplements
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* \author Alexander Boettcher
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* \author Norman Feske
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* \author Christian Helmuth
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*/
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/*
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* Copyright (C) 2013-2014 Genode Labs GmbH
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*
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* This file is distributed under the terms of the GNU General Public License
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* version 2.
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*/
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#ifndef _VCPU_H__
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#define _VCPU_H__
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/* Genode includes */
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#include <base/printf.h>
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#include <base/semaphore.h>
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#include <base/flex_iterator.h>
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#include <rom_session/connection.h>
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#include <timer_session/connection.h>
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#include <vmm/vcpu_thread.h>
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#include <vmm/vcpu_dispatcher.h>
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#include <vmm/printf.h>
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/* NOVA includes that come with Genode */
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#include <nova/syscalls.h>
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/* VirtualBox includes */
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#include <VBox/vmm/vm.h>
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#include <VBox/err.h>
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#include <VBox/vmm/pdmapi.h>
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/* Genode's VirtualBox includes */
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#include "sup.h"
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#include "guest_memory.h"
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#include "vmm_memory.h"
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/* Genode libc pthread binding */
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#include "thread.h"
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/* LibC includes */
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#include <setjmp.h>
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/*
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* VirtualBox stores segment attributes in Intel format using a 32-bit
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* value. NOVA represents the attributes in packet format using a 16-bit
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* value.
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*/
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static inline Genode::uint16_t sel_ar_conv_to_nova(Genode::uint32_t v)
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{
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return (v & 0xff) | ((v & 0x1f000) >> 4);
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}
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static inline Genode::uint32_t sel_ar_conv_from_nova(Genode::uint16_t v)
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{
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return (v & 0xff) | (((uint32_t )v << 4) & 0x1f000);
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}
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/*
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* Used to map mmio memory to VM
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*/
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extern "C" int MMIO2_MAPPED_SYNC(PVM pVM, RTGCPHYS GCPhys, size_t cbWrite,
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void **ppv);
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class Vcpu_handler : public Vmm::Vcpu_dispatcher<pthread>
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{
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private:
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Genode::Cap_connection _cap_connection;
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Vmm::Vcpu_other_pd _vcpu;
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Genode::addr_t _ec_sel = 0;
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void fpu_save(char * data) {
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Assert(!(reinterpret_cast<Genode::addr_t>(data) & 0xF));
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asm volatile ("fxsave %0" : "=m" (*data));
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}
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void fpu_load(char * data) {
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Assert(!(reinterpret_cast<Genode::addr_t>(data) & 0xF));
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asm volatile ("fxrstor %0" : : "m" (*data));
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}
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enum { IRQ_INJ_VALID_MASK = 0x80000000UL };
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protected:
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struct {
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Nova::mword_t mtd;
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unsigned intr_state;
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unsigned ctrl[2];
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} next_utcb;
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PVM _current_vm;
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PVMCPU _current_vcpu;
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void * _stack_reply;
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jmp_buf _env;
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void switch_to_hw(PCPUMCTX pCtx) {
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unsigned long value;
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if (!setjmp(_env)) {
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_stack_reply = reinterpret_cast<void *>(&value - 1);
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Nova::reply(_stack_reply);
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}
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}
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__attribute__((noreturn)) void _irq_window(unsigned cond)
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{
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Nova::Utcb * utcb = reinterpret_cast<Nova::Utcb *>(Thread_base::utcb());
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Assert(!(utcb->intr_state & 3));
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Assert(utcb->flags & X86_EFL_IF);
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Assert(!(utcb->inj_info & IRQ_INJ_VALID_MASK));
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if (irq_win(utcb)) {
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/* reset mtd to not transfer anything back by accident */
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utcb->mtd = 0;
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/* inject IRQ */
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inj_event(utcb, _current_vcpu, utcb->flags & X86_EFL_IF);
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Nova::reply(_stack_reply);
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}
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/* go back to re-compiler */
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longjmp(_env, 1);
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}
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__attribute__((noreturn)) void _default_handler()
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{
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Nova::Utcb * utcb = reinterpret_cast<Nova::Utcb *>(Thread_base::utcb());
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Assert(!(utcb->inj_info & IRQ_INJ_VALID_MASK));
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longjmp(_env, 1);
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}
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__attribute__((noreturn)) void _recall_handler()
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{
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/* take care - Mtd::EFL | Mtd::STA are solely written to utcb */
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Nova::Utcb * utcb = reinterpret_cast<Nova::Utcb *>(Thread_base::utcb());
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Assert(!(utcb->intr_state & 3));
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utcb->mtd = 0;
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inj_event(utcb, _current_vcpu, utcb->flags & X86_EFL_IF);
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Nova::reply(_stack_reply);
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}
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template <unsigned NPT_EPT>
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__attribute__((noreturn)) inline
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void _exc_memory(Genode::Thread_base * myself, Nova::Utcb * utcb,
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bool unmap, Genode::addr_t reason)
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{
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using namespace Nova;
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using namespace Genode;
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Assert(utcb->actv_state == 0);
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Assert(!(utcb->intr_state & 3));
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Assert(!(utcb->inj_info & IRQ_INJ_VALID_MASK));
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if (unmap) {
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PERR("unmap not implemented\n");
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Nova::reply(_stack_reply);
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}
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enum { MAP_SIZE = 0x1000UL };
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Flexpage_iterator fli;
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void *pv = guest_memory()->lookup_ram(reason, MAP_SIZE, fli);
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if (!pv) {
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/**
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* Check whether this is some mmio memory provided by VMM
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* we can map, e.g. VMMDev memory or framebuffer currently.
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*/
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int res = MMIO2_MAPPED_SYNC(_current_vm, reason, MAP_SIZE, &pv);
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if (pv && (res == VINF_SUCCESS))
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fli = Genode::Flexpage_iterator((addr_t)pv, MAP_SIZE,
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reason, MAP_SIZE, reason);
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else
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pv = 0;
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}
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/* emulator has to take over if fault region is not ram */
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if (!pv)
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longjmp(_env, 1);
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/* fault region is ram - so map it */
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enum {
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USER_PD = false, GUEST_PGT = true,
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READABLE = true, WRITEABLE = true, EXECUTABLE = true
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};
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Rights const permission(READABLE, WRITEABLE, EXECUTABLE);
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/* prepare utcb */
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utcb->set_msg_word(0);
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utcb->mtd = 0;
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/* add map items until no space is left on utcb anymore */
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bool res;
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do {
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Flexpage flexpage = fli.page();
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if (!flexpage.valid() || flexpage.log2_order < 12)
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break;
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/* touch memory - otherwise no mapping will take place */
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addr_t touch_me = flexpage.addr;
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while (touch_me < flexpage.addr + (1UL << flexpage.log2_order)) {
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touch_read(reinterpret_cast<unsigned char *>(touch_me));
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touch_me += 0x1000UL;
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}
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Crd crd = Mem_crd(flexpage.addr >> 12, flexpage.log2_order - 12,
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permission);
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res = utcb->append_item(crd, flexpage.hotspot, USER_PD, GUEST_PGT);
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} while (res);
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Nova::reply(_stack_reply);
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}
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/**
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* Shortcut for calling 'Vmm::Vcpu_dispatcher::register_handler'
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* with 'Vcpu_dispatcher' as template argument
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*/
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template <unsigned EV, void (Vcpu_handler::*FUNC)()>
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void _register_handler(Genode::addr_t exc_base, Nova::Mtd mtd)
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{
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if (!register_handler<EV, Vcpu_handler, FUNC>(exc_base, mtd))
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PERR("could not register handler %lx", exc_base + EV);
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}
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Vmm::Vcpu_other_pd &vcpu() { return _vcpu; }
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inline bool vbox_to_utcb(Nova::Utcb * utcb, VM *pVM, PVMCPU pVCpu)
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{
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PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
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using namespace Nova;
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if (utcb->ip != pCtx->rip) {
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utcb->mtd |= Mtd::EIP;
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utcb->ip = pCtx->rip;
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}
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if (utcb->sp != pCtx->rsp) {
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utcb->mtd |= Mtd::ESP;
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utcb->sp = pCtx->rsp;
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}
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if (utcb->ax != pCtx->rax || utcb->bx != pCtx->rbx ||
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utcb->cx != pCtx->rcx || utcb->dx != pCtx->rdx)
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{
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utcb->mtd |= Mtd::ACDB;
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utcb->ax = pCtx->rax;
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utcb->bx = pCtx->rbx;
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utcb->cx = pCtx->rcx;
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utcb->dx = pCtx->rdx;
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}
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if (utcb->bp != pCtx->rbp || utcb->si != pCtx->rsi ||
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utcb->di != pCtx->rdi)
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{
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utcb->mtd |= Mtd::EBSD;
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utcb->bp = pCtx->rbp;
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utcb->si = pCtx->rsi;
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utcb->di = pCtx->rdi;
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}
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if (utcb->flags != pCtx->rflags.u) {
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utcb->mtd |= Mtd::EFL;
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utcb->flags = pCtx->rflags.u;
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}
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if (utcb->sysenter_cs != pCtx->SysEnter.cs ||
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utcb->sysenter_sp != pCtx->SysEnter.esp ||
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utcb->sysenter_ip != pCtx->SysEnter.eip)
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{
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utcb->mtd |= Mtd::SYS;
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utcb->sysenter_cs = pCtx->SysEnter.cs;
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utcb->sysenter_sp = pCtx->SysEnter.esp;
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utcb->sysenter_ip = pCtx->SysEnter.eip;
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}
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if (utcb->dr7 != pCtx->dr[7]) {
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utcb->mtd |= Mtd::DR;
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utcb->dr7 = pCtx->dr[7];
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}
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if (utcb->cr0 != pCtx->cr0) {
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utcb->mtd |= Mtd::CR;
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utcb->cr0 = pCtx->cr0;
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}
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if (utcb->cr2 != pCtx->cr2) {
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utcb->mtd |= Mtd::CR;
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utcb->cr2 = pCtx->cr2;
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}
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if (utcb->cr3 != pCtx->cr3) {
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utcb->mtd |= Mtd::CR;
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utcb->cr3 = pCtx->cr3;
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}
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if (utcb->cr4 != pCtx->cr4) {
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utcb->mtd |= Mtd::CR;
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utcb->cr4 = pCtx->cr4;
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}
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if (utcb->idtr.limit != pCtx->idtr.cbIdt ||
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utcb->idtr.base != pCtx->idtr.pIdt)
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{
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utcb->mtd |= Mtd::IDTR;
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utcb->idtr.limit = pCtx->idtr.cbIdt;
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utcb->idtr.base = pCtx->idtr.pIdt;
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}
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if (utcb->gdtr.limit != pCtx->gdtr.cbGdt ||
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utcb->gdtr.base != pCtx->gdtr.pGdt)
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{
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utcb->mtd |= Mtd::GDTR;
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utcb->gdtr.limit = pCtx->gdtr.cbGdt;
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utcb->gdtr.base = pCtx->gdtr.pGdt;
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}
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if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)) {
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if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) {
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PERR("intr_state nothing !=");
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VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
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utcb->intr_state = 0;
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while (1) {}
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}
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}
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return true;
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}
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inline bool utcb_to_vbox(Nova::Utcb * utcb, VM *pVM, PVMCPU pVCpu)
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{
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PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
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pCtx->rip = utcb->ip;
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pCtx->rsp = utcb->sp;
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pCtx->rax = utcb->ax;
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pCtx->rbx = utcb->bx;
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pCtx->rcx = utcb->cx;
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pCtx->rdx = utcb->dx;
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pCtx->rbp = utcb->bp;
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pCtx->rsi = utcb->si;
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pCtx->rdi = utcb->di;
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pCtx->rflags.u = utcb->flags;
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pCtx->dr[7] = utcb->dr7;
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if (pCtx->SysEnter.cs != utcb->sysenter_cs)
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_CS, utcb->sysenter_cs);
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if (pCtx->SysEnter.esp != utcb->sysenter_sp)
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_ESP, utcb->sysenter_sp);
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if (pCtx->SysEnter.eip != utcb->sysenter_ip)
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CPUMSetGuestMsr(pVCpu, MSR_IA32_SYSENTER_EIP, utcb->sysenter_ip);
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if (pCtx->idtr.cbIdt != utcb->idtr.limit ||
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pCtx->idtr.pIdt != utcb->idtr.base)
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CPUMSetGuestIDTR(pVCpu, utcb->idtr.base, utcb->idtr.limit);
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if (pCtx->gdtr.cbGdt != utcb->gdtr.limit ||
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pCtx->gdtr.pGdt != utcb->gdtr.base)
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CPUMSetGuestGDTR(pVCpu, utcb->gdtr.base, utcb->gdtr.limit);
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if (pCtx->cr0 != utcb->cr0)
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CPUMSetGuestCR0(pVCpu, utcb->cr0);
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if (pCtx->cr2 != utcb->cr2)
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CPUMSetGuestCR2(pVCpu, utcb->cr2);
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if (pCtx->cr3 != utcb->cr3)
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CPUMSetGuestCR3(pVCpu, utcb->cr3);
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if (pCtx->cr4 != utcb->cr4)
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CPUMSetGuestCR4(pVCpu, utcb->cr4);
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VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
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/* tell rem compiler that FPU register changed XXX optimizations ? */
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CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM); /* redundant ? XXX */
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pVCpu->cpum.s.fUseFlags |= (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM); /* redundant ? XXX */
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if (utcb->intr_state != 0)
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EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
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else
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VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
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return true;
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}
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inline bool inj_event(Nova::Utcb * utcb, PVMCPU pVCpu, bool if_flag)
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{
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if (!TRPMHasTrap(pVCpu)) {
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if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI)) {
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PDBG("%u hoho", __LINE__);
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while (1) {}
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}
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if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC))) {
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if (!if_flag) {
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unsigned vector = 0;
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utcb->inj_info = 0x1000 | vector;
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utcb->mtd |= Nova::Mtd::INJ;
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} else
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if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)) {
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uint8_t irq;
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int rc = PDMGetInterrupt(pVCpu, &irq);
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Assert(RT_SUCCESS(rc));
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rc = TRPMAssertTrap(pVCpu, irq, TRPM_HARDWARE_INT);
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Assert(RT_SUCCESS(rc));
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} else
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Vmm::printf("pending interrupt blocked due to INHIBIT flag\n");
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}
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}
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/* can an interrupt be dispatched ? */
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if (!TRPMHasTrap(pVCpu) || !if_flag ||
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VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
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return false;
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#ifdef VBOX_STRICT
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if (TRPMHasTrap(pVCpu)) {
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uint8_t u8Vector;
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int const rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
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AssertRC(rc);
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}
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#endif
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/* interrupt can be dispatched */
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uint8_t u8Vector;
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TRPMEVENT enmType;
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SVM_EVENT Event;
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RTGCUINT u32ErrorCode;
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Event.au64[0] = 0;
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/* If a new event is pending, then dispatch it now. */
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int rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
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AssertRC(rc);
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Assert(enmType == TRPM_HARDWARE_INT);
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/* Clear the pending trap. */
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rc = TRPMResetTrap(pVCpu);
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AssertRC(rc);
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Event.n.u8Vector = u8Vector;
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Event.n.u1Valid = 1;
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Event.n.u32ErrorCode = u32ErrorCode;
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Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
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utcb->inj_info = Event.au64[0];
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utcb->inj_error = Event.n.u32ErrorCode;
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utcb->mtd |= Nova::Mtd::INJ;
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/*
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Vmm::printf("type:info:vector %x:%x:%x\n",
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Event.n.u3Type, utcb->inj_info, u8Vector);
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*/
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return true;
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}
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inline bool irq_win(Nova::Utcb * utcb)
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{
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Assert(!(VMCPU_FF_ISSET(_current_vcpu, VMCPU_FF_INHIBIT_INTERRUPTS)));
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uint32_t check_vm = VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST
|
|
| VM_FF_PGM_POOL_FLUSH_PENDING
|
|
| VM_FF_PDM_DMA;
|
|
uint32_t check_vcpu = VMCPU_FF_HWACCM_TO_R3_MASK
|
|
| VMCPU_FF_PGM_SYNC_CR3
|
|
| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
|
|
| VMCPU_FF_REQUEST;
|
|
|
|
if (VM_FF_ISPENDING(_current_vm, check_vm)
|
|
|| VMCPU_FF_ISPENDING(_current_vcpu, check_vcpu))
|
|
{
|
|
Assert(VM_FF_ISPENDING(_current_vm, VM_FF_HWACCM_TO_R3_MASK) ||
|
|
VMCPU_FF_ISPENDING(_current_vcpu,
|
|
VMCPU_FF_HWACCM_TO_R3_MASK));
|
|
|
|
Assert(!(RT_UNLIKELY(VM_FF_ISPENDING(_current_vm,
|
|
VM_FF_PGM_NO_MEMORY))));
|
|
|
|
return false;
|
|
}
|
|
|
|
/* Is in Realmode ? */
|
|
if (!(utcb->cr0 & X86_CR0_PE))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
virtual bool hw_load_state(Nova::Utcb *, VM *, PVMCPU) = 0;
|
|
virtual bool hw_save_state(Nova::Utcb *, VM *, PVMCPU) = 0;
|
|
|
|
public:
|
|
|
|
enum Exit_condition
|
|
{
|
|
SVM_NPT = 0xfc,
|
|
SVM_INVALID = 0xfd,
|
|
|
|
VCPU_STARTUP = 0xfe,
|
|
|
|
RECALL = 0xff,
|
|
EMULATE_INSTR = 0x100
|
|
};
|
|
|
|
|
|
Vcpu_handler(size_t stack_size, const pthread_attr_t *attr,
|
|
void *(*start_routine) (void *), void *arg,
|
|
Genode::Cpu_session * cpu_session)
|
|
:
|
|
Vmm::Vcpu_dispatcher<pthread>(stack_size, _cap_connection,
|
|
attr ? *attr : 0, start_routine, arg),
|
|
_vcpu(cpu_session),
|
|
_ec_sel(Genode::cap_map()->insert())
|
|
{ }
|
|
|
|
void start() {
|
|
_vcpu.start(_ec_sel);
|
|
}
|
|
|
|
void recall()
|
|
{
|
|
using namespace Nova;
|
|
|
|
if (ec_ctrl(EC_RECALL, _ec_sel) != NOVA_OK) {
|
|
PERR("recall failed");
|
|
Genode::Lock lock(Genode::Lock::LOCKED);
|
|
lock.lock();
|
|
}
|
|
}
|
|
|
|
inline void dump_register_state(PCPUMCTX pCtx)
|
|
{
|
|
PINF("pCtx");
|
|
PLOG("ip:sp:efl ax:bx:cx:dx:si:di %llx:%llx:%llx"
|
|
" %llx:%llx:%llx:%llx:%llx:%llx",
|
|
pCtx->rip, pCtx->rsp, pCtx->rflags.u, pCtx->rax, pCtx->rbx,
|
|
pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi);
|
|
|
|
PLOG("cs.attr.n.u4LimitHigh=0x%x", pCtx->cs.Attr.n.u4LimitHigh);
|
|
|
|
PLOG("cs base:limit:sel:ar %llx:%x:%x:%x", pCtx->cs.u64Base,
|
|
pCtx->cs.u32Limit, pCtx->cs.Sel, pCtx->cs.Attr.u);
|
|
PLOG("ds base:limit:sel:ar %llx:%x:%x:%x", pCtx->ds.u64Base,
|
|
pCtx->ds.u32Limit, pCtx->ds.Sel, pCtx->ds.Attr.u);
|
|
PLOG("es base:limit:sel:ar %llx:%x:%x:%x", pCtx->es.u64Base,
|
|
pCtx->es.u32Limit, pCtx->es.Sel, pCtx->es.Attr.u);
|
|
PLOG("fs base:limit:sel:ar %llx:%x:%x:%x", pCtx->fs.u64Base,
|
|
pCtx->fs.u32Limit, pCtx->fs.Sel, pCtx->fs.Attr.u);
|
|
PLOG("gs base:limit:sel:ar %llx:%x:%x:%x", pCtx->gs.u64Base,
|
|
pCtx->gs.u32Limit, pCtx->gs.Sel, pCtx->gs.Attr.u);
|
|
PLOG("ss base:limit:sel:ar %llx:%x:%x:%x", pCtx->ss.u64Base,
|
|
pCtx->ss.u32Limit, pCtx->ss.Sel, pCtx->ss.Attr.u);
|
|
|
|
PLOG("cr0:cr2:cr3:cr4 %llx:%llx:%llx:%llx",
|
|
pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4);
|
|
|
|
PLOG("ldtr base:limit:sel:ar %llx:%x:%x:%x", pCtx->ldtr.u64Base,
|
|
pCtx->ldtr.u32Limit, pCtx->ldtr.Sel, pCtx->ldtr.Attr.u);
|
|
PLOG("tr base:limit:sel:ar %llx:%x:%x:%x", pCtx->tr.u64Base,
|
|
pCtx->tr.u32Limit, pCtx->tr.Sel, pCtx->tr.Attr.u);
|
|
|
|
PLOG("gdtr base:limit %llx:%x", pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt);
|
|
PLOG("idtr base:limit %llx:%x", pCtx->idtr.pIdt, pCtx->idtr.cbIdt);
|
|
|
|
PLOG("dr 0:1:2:3:4:5:6:7 %llx:%llx:%llx:%llx:%llx:%llx:%llx:%llx",
|
|
pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
|
|
pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7]);
|
|
|
|
PLOG("sysenter cs:eip:esp %llx %llx %llx", pCtx->SysEnter.cs,
|
|
pCtx->SysEnter.eip, pCtx->SysEnter.esp);
|
|
}
|
|
|
|
inline void dump_register_state(Nova::Utcb * utcb)
|
|
{
|
|
PINF("utcb");
|
|
PLOG("ip:sp:efl ax:bx:cx:dx:si:di %lx:%lx:%lx"
|
|
" %lx:%lx:%lx:%lx:%lx:%lx",
|
|
utcb->ip, utcb->sp, utcb->flags, utcb->ax, utcb->bx,
|
|
utcb->cx, utcb->dx, utcb->si, utcb->di);
|
|
|
|
PLOG("cs base:limit:sel:ar %lx:%x:%x:%x", utcb->cs.base,
|
|
utcb->cs.limit, utcb->cs.sel, utcb->cs.ar);
|
|
PLOG("ds base:limit:sel:ar %lx:%x:%x:%x", utcb->ds.base,
|
|
utcb->ds.limit, utcb->ds.sel, utcb->ds.ar);
|
|
PLOG("es base:limit:sel:ar %lx:%x:%x:%x", utcb->es.base,
|
|
utcb->es.limit, utcb->es.sel, utcb->es.ar);
|
|
PLOG("fs base:limit:sel:ar %lx:%x:%x:%x", utcb->fs.base,
|
|
utcb->fs.limit, utcb->fs.sel, utcb->fs.ar);
|
|
PLOG("gs base:limit:sel:ar %lx:%x:%x:%x", utcb->gs.base,
|
|
utcb->gs.limit, utcb->gs.sel, utcb->gs.ar);
|
|
PLOG("ss base:limit:sel:ar %lx:%x:%x:%x", utcb->ss.base,
|
|
utcb->ss.limit, utcb->ss.sel, utcb->ss.ar);
|
|
|
|
PLOG("cr0:cr2:cr3:cr4 %lx:%lx:%lx:%lx",
|
|
utcb->cr0, utcb->cr2, utcb->cr3, utcb->cr4);
|
|
|
|
PLOG("ldtr base:limit:sel:ar %lx:%x:%x:%x", utcb->ldtr.base,
|
|
utcb->ldtr.limit, utcb->ldtr.sel, utcb->ldtr.ar);
|
|
PLOG("tr base:limit:sel:ar %lx:%x:%x:%x", utcb->tr.base,
|
|
utcb->tr.limit, utcb->tr.sel, utcb->tr.ar);
|
|
|
|
PLOG("gdtr base:limit %lx:%x", utcb->gdtr.base, utcb->gdtr.limit);
|
|
PLOG("idtr base:limit %lx:%x", utcb->idtr.base, utcb->idtr.limit);
|
|
|
|
PLOG("dr 7 %lx", utcb->dr7);
|
|
|
|
PLOG("sysenter cs:eip:esp %lx %lx %lx", utcb->sysenter_cs,
|
|
utcb->sysenter_ip, utcb->sysenter_sp);
|
|
|
|
PLOG("%x %x %x", utcb->intr_state, utcb->actv_state, utcb->mtd);
|
|
}
|
|
|
|
int run_hw(PVMR0 pVMR0, VMCPUID idCpu)
|
|
{
|
|
VM * pVM = reinterpret_cast<VM *>(pVMR0);
|
|
PVMCPU pVCpu = &pVM->aCpus[idCpu];
|
|
PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
|
|
|
Nova::Utcb *utcb = reinterpret_cast<Nova::Utcb *>(Thread_base::utcb());
|
|
|
|
Assert(Thread_base::utcb() == Thread_base::myself()->utcb());
|
|
|
|
/* take the utcb state prepared during the last exit */
|
|
utcb->mtd = next_utcb.mtd;
|
|
utcb->intr_state = next_utcb.intr_state;
|
|
utcb->actv_state = 0; /* XXX */
|
|
utcb->ctrl[0] = next_utcb.ctrl[0];
|
|
utcb->ctrl[1] = next_utcb.ctrl[1];
|
|
|
|
using namespace Nova;
|
|
|
|
/* check whether to inject interrupts */
|
|
inj_event(utcb, pVCpu, pCtx->rflags.u & X86_EFL_IF);
|
|
|
|
/* Transfer vCPU state from vBox to Nova format */
|
|
if (!vbox_to_utcb(utcb, pVM, pVCpu) ||
|
|
!hw_load_state(utcb, pVM, pVCpu)) {
|
|
|
|
PERR("loading vCPU state failed");
|
|
return VERR_INTERNAL_ERROR;
|
|
}
|
|
|
|
/*
|
|
* Flag vCPU to be "pokeable" by external events such as interrupts
|
|
* from virtual devices. Only if this flag is set, the
|
|
* 'vmR3HaltGlobal1NotifyCpuFF' function calls 'SUPR3CallVMMR0Ex'
|
|
* with VMMR0_DO_GVMM_SCHED_POKE as argument to indicate such
|
|
* events. This function, in turn, will recall the vCPU.
|
|
*/
|
|
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
|
|
|
|
/* write FPU state from pCtx to vCPU */
|
|
fpu_load(reinterpret_cast<char *>(&pCtx->fpu));
|
|
|
|
utcb->mtd |= Mtd::FPU;
|
|
|
|
_current_vm = pVM;
|
|
_current_vcpu = pVCpu;
|
|
|
|
/* switch to hardware accelerated mode */
|
|
switch_to_hw(pCtx);
|
|
|
|
Assert(utcb->actv_state == 0);
|
|
|
|
_current_vm = 0;
|
|
_current_vcpu = 0;
|
|
|
|
/* write FPU state of vCPU to pCtx */
|
|
fpu_save(reinterpret_cast<char *>(&pCtx->fpu));
|
|
|
|
// CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
|
|
|
|
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
|
|
|
|
/* Transfer vCPU state from Nova to vBox format */
|
|
if (!utcb_to_vbox(utcb, pVM, pVCpu) ||
|
|
!hw_save_state(utcb, pVM, pVCpu)) {
|
|
|
|
PERR("saving vCPU state failed");
|
|
return VERR_INTERNAL_ERROR;
|
|
}
|
|
|
|
/* reset message transfer descriptor for next invocation */
|
|
next_utcb.mtd = 0;
|
|
next_utcb.intr_state = utcb->intr_state;
|
|
next_utcb.ctrl[0] = utcb->ctrl[0];
|
|
next_utcb.ctrl[1] = utcb->ctrl[1];
|
|
|
|
if (next_utcb.intr_state & 3) {
|
|
next_utcb.intr_state &= ~3U;
|
|
next_utcb.mtd |= Mtd::STA;
|
|
}
|
|
|
|
return VINF_EM_RAW_EMULATE_INSTR;
|
|
}
|
|
};
|
|
|
|
#endif /* _VCPU_H__ */
|