152 lines
4.1 KiB
C++
152 lines
4.1 KiB
C++
/*
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* \brief Base EMAC driver for the Xilinx EMAC PS used on Zynq devices
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* \author Timo Wischer
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* \date 2015-03-10
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__NIC__GEM__SYSTEM_CONTROL_H_
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#define _INCLUDE__DRIVERS__NIC__GEM__SYSTEM_CONTROL_H_
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/* Genode includes */
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#include <os/attached_mmio.h>
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#include <timer_session/connection.h>
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#include <drivers/board_base.h>
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using namespace Genode;
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class System_control : private Genode::Attached_mmio
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{
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private:
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struct Lock : Register<0x4, 32> {
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enum { MAGIC = 0x767B };
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};
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struct Unlock : Register<0x8, 32> {
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enum { MAGIC = 0xDF0D };
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};
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struct Gem0_rclk_ctrl : Register<0x138, 32> { };
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struct Gem0_clk_ctrl : Register<0x140, 32> { };
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struct Mio_pin_16 : Register<0x740, 32> {
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struct Tri_state_enable : Bitfield<0, 1> {};
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struct Level_0_mux : Bitfield<1, 1> {
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enum { ETH0 = 0b1 };
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};
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struct Fast_cmos_edge : Bitfield<8, 1> {};
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struct IO_type : Bitfield<9, 3> {
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enum { LVCMOS18 = 0b001 };
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};
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static access_t FAST_LVCMOS18_ETH0() {
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return Fast_cmos_edge::bits(1) |
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IO_type::bits(IO_type::LVCMOS18) |
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Level_0_mux::bits(Level_0_mux::ETH0);
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}
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static access_t FAST_LVCMOS18_ETH0_TRISTATE() {
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return FAST_LVCMOS18_ETH0() |
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Tri_state_enable::bits(1);
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}
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};
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struct Mio_pin_17 : Register<0x744, 32> { };
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struct Mio_pin_18 : Register<0x748, 32> { };
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struct Mio_pin_19 : Register<0x74C, 32> { };
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struct Mio_pin_20 : Register<0x750, 32> { };
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struct Mio_pin_21 : Register<0x754, 32> { };
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struct Mio_pin_22 : Register<0x758, 32> { };
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struct Mio_pin_23 : Register<0x75C, 32> { };
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struct Mio_pin_24 : Register<0x760, 32> { };
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struct Mio_pin_25 : Register<0x764, 32> { };
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struct Mio_pin_26 : Register<0x768, 32> { };
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struct Mio_pin_27 : Register<0x76C, 32> { };
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struct Mio_pin_52 : Register<0x7D0, 32> {
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struct Level_3_mux : Bitfield<5, 3> {
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enum { MDIO0 = 0b100 };
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};
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static access_t LVCMOS18_MDIO0() {
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return Mio_pin_16::IO_type::bits(Mio_pin_16::IO_type::LVCMOS18) |
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Level_3_mux::bits(Level_3_mux::MDIO0);
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}
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};
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struct Mio_pin_53 : Register<0x7D4, 32> { };
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struct Gpio_b_ctrl : Register<0xB00, 32> {
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struct Vref_enable : Bitfield<0, 1> {};
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};
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class Lock_guard
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{
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private:
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System_control& _sys_ctrl;
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void _unlock() { _sys_ctrl.write<Unlock>(Unlock::MAGIC); }
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void _lock() { _sys_ctrl.write<Lock>(Lock::MAGIC); }
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public:
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Lock_guard(System_control& sys_ctrl) : _sys_ctrl(sys_ctrl)
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{
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_unlock();
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}
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~Lock_guard()
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{
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_lock();
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}
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};
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unsigned int old_data[0x300];
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public:
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System_control() :
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Attached_mmio(Board_base::MMIO_1_BASE, 0xB80)
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{
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Lock_guard lock(*this);
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write<Mio_pin_16>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_17>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_18>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_19>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_20>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_21>(Mio_pin_16::FAST_LVCMOS18_ETH0());
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write<Mio_pin_22>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_23>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_24>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_25>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_26>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_27>(Mio_pin_16::FAST_LVCMOS18_ETH0_TRISTATE());
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write<Mio_pin_52>(Mio_pin_52::LVCMOS18_MDIO0());
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write<Mio_pin_53>(Mio_pin_52::LVCMOS18_MDIO0());
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// TODO possibly not needed because uboot do not enable this register
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/* enable internel VRef */
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write<Gpio_b_ctrl>(Gpio_b_ctrl::Vref_enable::bits(1));
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}
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void set_clk(uint32_t clk, uint32_t rclk)
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{
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Lock_guard lock(*this);
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write<Gem0_clk_ctrl>(clk);
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write<Gem0_rclk_ctrl>(rclk);
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static Timer::Connection timer;
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timer.msleep(100);
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}
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};
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#endif /* _INCLUDE__DRIVERS__NIC__GEM__SYSTEM_CONTROL_H_ */
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