539 lines
13 KiB
C++
539 lines
13 KiB
C++
/*
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* \brief Base EMAC driver for the Xilinx EMAC PS used on Zynq devices
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* \author Timo Wischer
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* \date 2015-03-10
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__NIC__XILINX_EMACPS_BASE_H_
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#define _INCLUDE__DRIVERS__NIC__XILINX_EMACPS_BASE_H_
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/* Genode includes */
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#include <os/attached_mmio.h>
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#include <nic_session/nic_session.h>
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#include <nic/driver.h>
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#include <timer_session/connection.h>
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#include "system_control.h"
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#include "tx_buffer_descriptor.h"
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#include "rx_buffer_descriptor.h"
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#include "marvell_phy.h"
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namespace Genode
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{
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/**
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* Base driver Xilinx EMAC PS module
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*/
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class Cadence_gem : private Genode::Attached_mmio, public Nic::Driver, public Phyio
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{
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private:
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/**
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* Control register
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*/
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struct Control : Register<0x00, 32>
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{
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struct Local_loopback : Bitfield<1, 1> {};
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struct Rx_en : Bitfield<2, 1> {};
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struct Tx_en : Bitfield<3, 1> {};
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struct Mgmt_port_en : Bitfield<4, 1> {};
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struct Clear_statistics : Bitfield<5, 1> {};
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struct Start_tx : Bitfield<9, 1> {};
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static access_t init() {
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return Mgmt_port_en::bits(1) |
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Tx_en::bits(1) |
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Rx_en::bits(1);
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}
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static access_t start_tx() {
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return (init() | Start_tx::bits(1));
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}
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};
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/**
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* Config register
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*/
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struct Config : Register<0x04, 32>
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{
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struct Speed_100 : Bitfield<0, 1> {};
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struct Full_duplex : Bitfield<1, 1> {};
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struct Copy_all : Bitfield<4, 1> {};
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struct No_broadcast : Bitfield<5, 1> {};
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struct Multi_hash_en : Bitfield<6, 1> {};
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struct Gige_en : Bitfield<10, 1> {};
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struct Fcs_remove : Bitfield<17, 1> {};
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struct Mdc_clk_div : Bitfield<18, 3> {
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enum {
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DIV_32 = 0b010,
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DIV_224 = 0b111,
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};
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};
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struct Ignore_rx_fcs : Bitfield<26, 1> {};
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};
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/**
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* Status register
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*/
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struct Status : Register<0x08, 32>
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{
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struct Phy_mgmt_idle : Bitfield<2, 1> {};
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};
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/**
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* DMA Config register
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*/
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struct Dma_config : Register<0x10, 32>
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{
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struct Rx_pktbuf_memsz_sel : Bitfield<8, 2> {
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enum {
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SPACE_8KB = 0x3,
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};
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};
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struct Tx_pktbuf_memsz_sel : Bitfield<10, 1> {
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enum {
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SPACE_4KB = 0x1,
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};
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};
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struct Ahb_mem_rx_buf_size : Bitfield<16, 8> {
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enum {
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BUFFER_1600B = 0x19,
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};
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};
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static access_t init()
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{
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return Ahb_mem_rx_buf_size::bits(Ahb_mem_rx_buf_size::BUFFER_1600B) |
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Rx_pktbuf_memsz_sel::bits(Rx_pktbuf_memsz_sel::SPACE_8KB) |
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Tx_pktbuf_memsz_sel::bits(Tx_pktbuf_memsz_sel::SPACE_4KB);
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}
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// TODO possibly enable transmition check sum offloading
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};
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/**
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* Tx_Status register
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*/
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struct Tx_status : Register<0x14, 32>
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{
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struct Tx_complete : Bitfield<5, 1> {};
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struct Tx_go : Bitfield<3, 1> {};
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};
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/**
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* Receiving queue base addresse register
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*/
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struct Rx_qbar : Register<0x18, 32>
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{
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struct Addr : Bitfield<0, 32> {};
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};
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/**
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* Transmition queue base addresse register
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*/
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struct Tx_qbar : Register<0x1C, 32>
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{
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struct Addr : Bitfield<0, 32> {};
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};
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/**
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* Receive status register
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*/
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struct Rx_status : Register<0x20, 32>
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{
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struct Frame_reveived : Bitfield<1, 1> {};
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struct Buffer_not_available : Bitfield<0, 1> {};
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};
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/**
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* Interrupt status register
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*/
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struct Interrupt_status : Register<0x24, 32>
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{
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struct Rx_used_read : Bitfield<3, 1> {};
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struct Rx_complete : Bitfield<1, 1> {};
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};
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/**
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* Interrupt enable register
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*/
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struct Interrupt_enable : Register<0x28, 32>
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{
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struct Rx_complete : Bitfield<1, 1> {};
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};
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/**
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* Interrupt disable register
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*/
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struct Interrupt_disable : Register<0x2C, 32>
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{
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struct Rx_complete : Bitfield<1, 1> {};
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};
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/**
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* PHY maintenance register
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*/
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struct Phy_maintenance : Register<0x34, 32>
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{
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struct Clause_22 : Bitfield<30, 1> {};
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struct Operation : Bitfield<28, 2> {
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enum Type {
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READ = 0b10,
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WRITE = 0b01
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};
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};
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struct Phy_addr : Bitfield<23, 5> {};
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struct Reg_addr : Bitfield<18, 5> {};
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struct Must_10 : Bitfield<16, 2> {
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enum { INIT = 0b10 };
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};
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struct Data : Bitfield<0, 16> {};
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};
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/**
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* MAC hash register
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*/
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struct Hash_register : Register<0x80, 64>
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{
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struct Low_hash : Bitfield<0, 32> { };
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struct High_hash : Bitfield<32, 16> { };
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};
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/**
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* MAC Addresse
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*/
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struct Mac_addr_1 : Register<0x88, 64>
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{
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struct Low_addr : Bitfield<0, 32> { };
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struct High_addr : Bitfield<32, 16> { };
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};
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/**
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* Counter for the successfully transmitted frames
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*/
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struct Frames_transmitted : Register<0x108, 32>
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{
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struct Counter : Bitfield<0, 32> { };
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};
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/**
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* Counter for the successfully received frames
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*/
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struct Frames_received : Register<0x158, 32>
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{
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struct Counter : Bitfield<0, 32> { };
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};
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/**
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* Counter for the successfully received frames
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*/
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struct Rx_overrun_errors : Register<0x1A4, 32>
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{
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struct Counter : Bitfield<0, 10> { };
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};
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class Phy_timeout_for_idle : public Genode::Exception {};
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class Unkown_ethernet_speed : public Genode::Exception {};
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Timer::Connection _timer;
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System_control _sys_ctrl;
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Tx_buffer_descriptor _tx_buffer;
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Rx_buffer_descriptor _rx_buffer;
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Nic::Rx_buffer_alloc& _rx_buffer_alloc;
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Nic::Driver_notification &_notify;
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enum { IRQ_STACK_SIZE = 4096 };
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const Genode::Irq_activation _irq_activation;
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Marvel_phy _phy;
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void _init()
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{
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// TODO checksum offloading and pause frames
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/* see 16.3.2 Configure the Controller */
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/* 1. Program the Network Configuration register (gem.net_cfg) */
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write<Config>(
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Config::Speed_100::bits(1) |
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Config::Full_duplex::bits(1) |
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Config::Multi_hash_en::bits(1) |
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Config::Mdc_clk_div::bits(Config::Mdc_clk_div::DIV_32) |
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Config::Fcs_remove::bits(1)
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);
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/* 2. set mac address */
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Nic::Mac_address mac;
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mac.addr[5] = 0x12;
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mac.addr[4] = 0x34;
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mac.addr[3] = 0x56;
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mac.addr[2] = 0x78;
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mac.addr[1] = 0x9A;
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mac.addr[0] = 0xBC;
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mac_address(mac);
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write<Rx_qbar>( _rx_buffer.phys_addr() );
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write<Tx_qbar>( _tx_buffer.phys_addr() );
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/* 3. Program the DMA Configuration register (gem.dma_cfg) */
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write<Dma_config>( Dma_config::init() );
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/*
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* 4. Program the Network Control Register (gem.net_ctrl)
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* Enable MDIO, transmitter and receiver
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*/
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write<Control>(Control::init());
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_phy.init();
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/* change emac clocks depending on phy autonegation result */
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uint32_t rclk = 0;
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uint32_t clk = 0;
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switch (_phy.eth_speed()) {
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case SPEED_1000:
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write<Config::Gige_en>(1);
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rclk = (0 << 4) | (1 << 0);
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clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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case SPEED_100:
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write<Config::Gige_en>(0);
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write<Config::Speed_100>(1);
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rclk = 1 << 0;
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clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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case SPEED_10:
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write<Config::Gige_en>(0);
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write<Config::Speed_100>(0);
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rclk = 1 << 0;
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/* FIXME untested */
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clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
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break;
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default:
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throw Unkown_ethernet_speed();
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}
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_sys_ctrl.set_clk(clk, rclk);
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/* 16.3.6 Configure Interrupts */
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write<Interrupt_enable>(Interrupt_enable::Rx_complete::bits(1));
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}
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void _deinit()
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{
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/* 16.3.1 Initialize the Controller */
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/* Disable all interrupts */
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write<Interrupt_disable>(0x7FFFEFF);
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/* Disable the receiver & transmitter */
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write<Control>(0);
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write<Control>(Control::Clear_statistics::bits(1));
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write<Tx_status>(0xFF);
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write<Rx_status>(0x0F);
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write<Phy_maintenance>(0);
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write<Rx_qbar>(0);
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write<Tx_qbar>(0);
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/* Clear the Hash registers for the mac address
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* pointed by AddressPtr
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*/
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write<Hash_register>(0);
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}
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void _mdio_wait()
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{
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uint32_t timeout = 200;
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/* Wait till MDIO interface is ready to accept a new transaction. */
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while (!read<Status::Phy_mgmt_idle>()) {
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if (timeout <= 0) {
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PWRN("%s: Timeout\n", __func__);
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throw Phy_timeout_for_idle();
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}
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_timer.msleep(1);
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timeout--;
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}
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}
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void _phy_setup_op(const uint8_t phyaddr, const uint8_t regnum, const uint16_t data, const Phy_maintenance::Operation::Type op)
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{
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_mdio_wait();
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/* Write mgtcr and wait for completion */
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write<Phy_maintenance>(
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Phy_maintenance::Clause_22::bits(1) |
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Phy_maintenance::Operation::bits(op) |
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Phy_maintenance::Phy_addr::bits(phyaddr) |
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Phy_maintenance::Reg_addr::bits(regnum) |
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Phy_maintenance::Must_10::bits(Phy_maintenance::Must_10::INIT) |
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Phy_maintenance::Data::bits(data) );
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_mdio_wait();
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}
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public:
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/**
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* Constructor
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*
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* \param base MMIO base address
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*/
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Cadence_gem(addr_t const base, size_t const size, const int irq, Nic::Rx_buffer_alloc& alloc,
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Nic::Driver_notification ¬ify) :
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Genode::Attached_mmio(base, size),
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_rx_buffer_alloc(alloc),
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_notify(notify),
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_irq_activation(irq, *this, IRQ_STACK_SIZE),
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_phy(*this)
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{
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_deinit();
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_init();
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}
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~Cadence_gem()
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{
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// TODO dsiable tx and rx and clean up irq registration
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_deinit();
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}
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void phy_write(const uint8_t phyaddr, const uint8_t regnum, const uint16_t data)
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{
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_phy_setup_op(phyaddr, regnum, data, Phy_maintenance::Operation::WRITE);
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}
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void phy_read(const uint8_t phyaddr, const uint8_t regnum, uint16_t& data)
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{
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_phy_setup_op(phyaddr, regnum, 0, Phy_maintenance::Operation::READ);
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data = read<Phy_maintenance::Data>();
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}
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void mac_address(const Nic::Mac_address mac)
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{
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const uint32_t* const low_addr_pointer = reinterpret_cast<const uint32_t*>(&mac.addr[0]);
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const uint16_t* const high_addr_pointer = reinterpret_cast<const uint16_t*>(&mac.addr[4]);
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write<Mac_addr_1::Low_addr>(*low_addr_pointer);
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write<Mac_addr_1::High_addr>(*high_addr_pointer);
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}
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/***************************
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** Nic::Driver interface **
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***************************/
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virtual Nic::Mac_address mac_address()
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{
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Nic::Mac_address mac;
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uint32_t* const low_addr_pointer = reinterpret_cast<uint32_t*>(&mac.addr[0]);
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uint16_t* const high_addr_pointer = reinterpret_cast<uint16_t*>(&mac.addr[4]);
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*low_addr_pointer = read<Mac_addr_1::Low_addr>();
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*high_addr_pointer = read<Mac_addr_1::High_addr>();
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return mac;
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}
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virtual bool link_state()
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{
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/* XXX return always true for now */
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return true;
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}
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virtual void tx(char const *packet, Genode::size_t size)
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{
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_tx_buffer.add_to_queue(packet, size);
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write<Control>(Control::start_tx());
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}
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/******************************
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** Irq_activation interface **
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******************************/
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virtual void handle_irq(int irq_number)
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{
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/* 16.3.9 Receiving Frames */
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/* read interrupt status, to detect the interrupt reasone */
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const Interrupt_status::access_t status = read<Interrupt_status>();
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const Rx_status::access_t rxStatus = read<Rx_status>();
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if ( Interrupt_status::Rx_complete::get(status) ) {
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while (_rx_buffer.package_available()) {
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// TODO use this buffer directly as the destination for the DMA controller
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// to minimize the overrun errors
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const size_t buffer_size = _rx_buffer.package_length();
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char* const buffer = static_cast<char*>( _rx_buffer_alloc.alloc(buffer_size) );
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/*
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* copy data from rx buffer to new allocated buffer.
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* Has to be copied,
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* because the extern allocater possibly is using the cache.
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*/
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if ( _rx_buffer.get_package(buffer, buffer_size) != buffer_size ) {
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PWRN("Package not fully copiied. Package ignored.");
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return;
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}
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/* clearing error flags */
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write<Interrupt_status::Rx_used_read>(1);
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write<Rx_status::Buffer_not_available>(1);
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/* comit buffer to system services */
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_rx_buffer_alloc.submit();
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}
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/* check, if there was lost some packages */
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const uint16_t lost_packages = read<Rx_overrun_errors::Counter>();
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if (lost_packages > 0) {
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PWRN("%d packages lost (%d packages successfully received)!",
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lost_packages, read<Frames_received>());
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}
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/* reset reveive complete interrupt */
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write<Rx_status>(Rx_status::Frame_reveived::bits(1));
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write<Interrupt_status>(Interrupt_status::Rx_complete::bits(1));
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} else {
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PWRN("IRQ %d with unkown reasone recevied (status: %08x).", irq_number, status);
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}
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}
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};
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}
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#endif /* _INCLUDE__DRIVERS__NIC__XILINX_EMACPS_BASE_H_ */
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