127 lines
3.4 KiB
C++
127 lines
3.4 KiB
C++
/*
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* \brief VMM mmio abstractions
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* \author Stefan Kalkowski
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* \date 2019-07-18
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <cpu.h>
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#include <mmio.h>
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using namespace Vmm;
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Mmio_register::Register Mmio_register::read(Address_range & access, Cpu & cpu)
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{
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if (_type == WO)
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throw Exception("Invalid read access to register ",
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_name, " ", access);
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using namespace Genode;
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switch (access.size) {
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case 1: return *(uint8_t*) ((addr_t)&_value + access.start);
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case 2: return *(uint16_t*) ((addr_t)&_value + access.start);
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case 4: return *(uint32_t*) ((addr_t)&_value + access.start);
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case 8: return _value;
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default: return 0;
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}
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}
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void Mmio_register::write(Address_range & access, Cpu & cpu, Register value)
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{
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if (_type == RO)
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throw Exception("Invalid write access to register ",
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_name, " ", access);
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using namespace Genode;
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switch (access.size) {
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case 1: *((uint8_t*) ((addr_t)&_value + access.start)) = value;
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case 2: *((uint16_t*) ((addr_t)&_value + access.start)) = value;
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case 4: *((uint32_t*) ((addr_t)&_value + access.start)) = value;
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case 8: _value = value;
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}
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}
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Mmio_register::Register Mmio_register::value() { return _value; }
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void Mmio_register::set(Register value) { _value = value; }
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Mmio_device::Register Mmio_device::read(Address_range & access, Cpu & cpu)
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{
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Mmio_register & reg = _registers.get<Mmio_register>(access);
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Address_range ar(access.start - reg.start, access.size);
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return reg.read(ar, cpu);
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}
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void Mmio_device::write(Address_range & access, Cpu & cpu, Register value)
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{
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Mmio_register & reg = _registers.get<Mmio_register>(access);
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Address_range ar(access.start - reg.start, access.size);
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reg.write(ar, cpu, value);
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}
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void Mmio_device::add(Mmio_register & reg) { _registers.add(reg); }
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void Vmm::Mmio_bus::handle_memory_access(Vmm::Cpu & cpu)
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{
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using namespace Genode;
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Cpu::State & state = cpu.state();
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struct Iss : Cpu::Esr
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{
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struct Write : Bitfield<6, 1> {};
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struct Register : Bitfield<16, 5> {};
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struct Sign_extend : Bitfield<21, 1> {};
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struct Access_size : Bitfield<22, 2> {
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enum { BYTE, HALFWORD, WORD, DOUBLEWORD }; };
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struct Valid : Bitfield<24, 1> {};
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static bool valid(access_t v) {
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return Valid::get(v) && !Sign_extend::get(v); }
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static bool write(access_t v) { return Write::get(v); }
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static unsigned r(access_t v) { return Register::get(v); }
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};
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if (!Iss::valid(state.esr_el2))
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throw Exception("Mmio_bus: unknown ESR=", Genode::Hex(state.esr_el2));
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bool wr = Iss::Write::get(state.esr_el2);
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unsigned idx = Iss::Register::get(state.esr_el2);
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uint64_t ipa = ((uint64_t)state.hpfar_el2 << 8)
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+ (state.far_el2 & ((1 << 12) - 1));
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uint64_t width = 1 << Iss::Access_size::get(state.esr_el2);
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try {
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Address_range bus_range(ipa, width);
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Mmio_device & dev = get<Mmio_device>(bus_range);
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Address_range dev_range(ipa - dev.start,width);
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if (wr) {
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dev.write(dev_range, cpu, (idx == 31) ? 0 : state.r[idx]);
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} else {
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if (idx > 30)
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throw Exception("Wrong register index when reading ", bus_range);
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state.r[idx] = dev.read(dev_range, cpu);
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}
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} catch(Exception & e) {
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Genode::warning(e);
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Genode::warning("Will ignore invalid bus access (IPA=",
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Genode::Hex(ipa), ")");
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}
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}
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