441 lines
13 KiB
C++
441 lines
13 KiB
C++
/*
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* \brief VMM ARM Generic Interrupt Controller device model
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* \author Stefan Kalkowski
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* \date 2019-08-05
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__SERVER__VMM__GIC_H_
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#define _SRC__SERVER__VMM__GIC_H_
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#include <mmio.h>
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#include <base/env.h>
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#include <drivers/defs/arm_v7.h>
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#include <util/list.h>
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#include <util/register.h>
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#include <util/reconstructible.h>
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namespace Vmm { class Gic; }
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class Vmm::Gic : public Vmm::Mmio_device
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{
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public:
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enum Irqs {
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MAX_SGI = 16,
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MAX_PPI = 16,
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MAX_SPI = 992,
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MAX_IRQ = 1020,
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SPURIOUS = 1023,
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};
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class Irq : public Genode::List<Irq>::Element
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{
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public:
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struct List : Genode::List<Irq>
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{
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void insert(Irq & irq);
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Irq * highest_enabled();
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};
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struct Irq_handler {
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virtual void eoi() {};
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virtual void enabled() {};
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virtual void disabled() {};
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};
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enum Type { SGI, PPI, SPI };
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enum State { INACTIVE, ACTIVE, PENDING, ACTIVE_PENDING };
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enum Config { LEVEL, EDGE };
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Irq(unsigned num, Type t, List &pending_list);
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bool enabled() const;
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bool active() const;
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bool pending() const;
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bool level() const;
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unsigned number() const;
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Genode::uint8_t priority() const;
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Genode::uint8_t target() const;
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void enable();
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void disable();
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void activate();
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void deactivate();
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void assert();
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void deassert();
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void level(bool l);
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void priority(Genode::uint8_t p);
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void target(Genode::uint8_t t);
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void handler(Irq_handler & handler);
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private:
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Irq(Irq const &);
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Irq &operator = (Irq const &);
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bool _enabled { false };
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Type _type { SPI };
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State _state { INACTIVE };
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Config _config { LEVEL };
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unsigned _num { 0 };
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Genode::uint8_t _prio { 0 };
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Genode::uint8_t _target { 1 };
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List & _pending_list;
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Irq_handler * _handler { nullptr };
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};
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struct Irq_reg: Mmio_register
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{
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unsigned const irq_count;
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virtual Register read(Irq & irq) { return 0; }
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virtual void write(Irq & irq, Register reg) { }
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Register read(Address_range & access, Cpu&) override;
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void write(Address_range & access, Cpu&, Register value) override;
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Irq_reg(Mmio_register::Name name,
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Mmio_register::Type type,
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Genode::uint64_t start,
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unsigned bits_per_irq,
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unsigned irq_count)
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: Mmio_register(name, type, start, bits_per_irq*irq_count/8),
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irq_count(irq_count) {}
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};
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class Gicd_banked
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{
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public:
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Irq & irq(unsigned num);
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void handle_irq();
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bool pending_irq();
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Gicd_banked(Cpu & cpu, Gic & gic, Mmio_bus & bus);
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private:
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Cpu & _cpu;
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Gic & _gic;
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Genode::Constructible<Irq> _sgi[MAX_SGI];
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Genode::Constructible<Irq> _ppi[MAX_PPI];
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Irq::List _pending_list;
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struct Redistributor : Mmio_device
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{
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unsigned cpu_id;
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bool last;
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Mmio_register gicr_ctlr { "GICR_CTLR", Mmio_register::RO,
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0x0, 4, 0b10010 };
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Mmio_register gicr_typer { "GICR_TYPER", Mmio_register::RO,
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0x8, 8, (Genode::uint64_t)cpu_id<<32 | cpu_id<<8 | (last ? 1<<4 : 0) };
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Mmio_register gicr_waker { "GICR_WAKER", Mmio_register::RO,
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0x14, 4, 0 };
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Mmio_register gicr_pidr2 { "GICR_PIDR2", Mmio_register::RO,
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0xffe8, 4, (3<<4) };
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Mmio_register gicr_igroupr0 { "GICR_IGROUPR0", Mmio_register::RO,
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0x10080, 4, 0 };
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struct Gicr_isenabler0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.enabled(); }
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void write(Irq & irq, Register v) { if (v) irq.enable(); }
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Gicr_isenabler0()
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: Irq_reg("GICR_ISENABLER0", Mmio_register::RW, 0x10100, 1, 32) {}
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} gicr_isenabler0;
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struct Gicr_icenabler0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.enabled(); }
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void write(Irq & irq, Register v) { if (v) irq.disable(); }
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Gicr_icenabler0()
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: Irq_reg("GICR_ICENABLER0", Mmio_register::RW, 0x10180, 1, 32) {}
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} gicr_icenabler0;
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struct Gicr_ispendr0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.pending(); }
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void write(Irq & irq, Register v) { if (v) irq.assert(); }
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Gicr_ispendr0()
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: Irq_reg("GICR_ISPENDR0", Mmio_register::RW, 0x10200, 1, 32) {}
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} gicr_ispendr0;
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struct Gicr_icpendr0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.pending(); }
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void write(Irq & irq, Register v) { if (v) irq.deassert(); }
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Gicr_icpendr0()
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: Irq_reg("GICR_ICPENDR0", Mmio_register::RW, 0x10280, 1, 32) {}
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} gicr_icpendr0;
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struct Gicr_isactiver0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.active(); }
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void write(Irq & irq, Register v) { if (v) irq.activate(); }
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Gicr_isactiver0()
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: Irq_reg("GICR_ISACTIVER0", Mmio_register::RW, 0x10300, 1, 32) {}
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} gicr_isactiver0;
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struct Gicr_icactiver0 : Irq_reg
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{
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Register read(Irq & irq) { return irq.active(); }
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void write(Irq & irq, Register v) { if (v) irq.deactivate(); }
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Gicr_icactiver0()
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: Irq_reg("GICR_ICACTIVER0", Mmio_register::RW, 0x10380, 1, 32) {}
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} gicr_icactiver0;
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struct Gicr_ipriorityr : Irq_reg
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{
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Register read(Irq & irq) { return irq.priority(); }
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void write(Irq & irq, Register v) { irq.priority(v); }
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Gicr_ipriorityr()
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: Irq_reg("GICR_IPRIORITYR", Mmio_register::RW, 0x10400, 8, 32) {}
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} gicr_ipriorityr;
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struct Gicr_icfgr : Irq_reg
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{
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Register read(Irq & irq) { return irq.level() ? 0 : 1; }
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void write(Irq & irq, Register v) { irq.level(!v); }
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Gicr_icfgr()
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: Irq_reg("GICR_ICFGR", Mmio_register::RW, 0x10c00, 8, 32) {}
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} gicr_icfgr;
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Redistributor(const Genode::uint64_t addr,
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const Genode::uint64_t size,
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unsigned cpu_id,
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bool last)
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: Mmio_device("GICR", addr, size), cpu_id(cpu_id), last(last)
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{
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add(gicr_ctlr);
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add(gicr_typer);
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add(gicr_waker);
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add(gicr_pidr2);
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add(gicr_igroupr0);
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add(gicr_isenabler0);
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add(gicr_icenabler0);
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add(gicr_ispendr0);
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add(gicr_icpendr0);
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add(gicr_isactiver0);
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add(gicr_icactiver0);
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add(gicr_ipriorityr);
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add(gicr_icfgr);
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}
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};
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Genode::Constructible<Redistributor> _rdist;
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};
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Gic(const char * const name,
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const Genode::uint64_t addr,
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const Genode::uint64_t size,
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Mmio_bus & bus,
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Genode::Env & env);
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private:
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friend struct Gicd_banked;
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Genode::Constructible<Irq> _spi[MAX_SPI];
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Irq::List _pending_list;
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unsigned _cpu_cnt { 2 }; /* FIXME: smp support */
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unsigned _version { 3 }; /* FIXME: version support */
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struct Gicd_ctlr : Genode::Register<32>, Mmio_register
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{
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struct Enable : Bitfield<0, 1> {};
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struct Disable : Bitfield<6, 1> {};
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void write(Address_range & access, Cpu & cpu,
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Mmio_register::Register value) override
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{
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access_t v = value;
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Disable::set(v, 0);
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Mmio_register::write(access, cpu, v);
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}
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Gicd_ctlr()
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: Mmio_register("GICD_CTLR", Mmio_register::RW, 0, 4, 0) {}
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} _ctrl;
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struct Gicd_typer : Genode::Register<32>, Mmio_register
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{
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struct It_lines_number : Bitfield<0, 5> {};
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struct Cpu_number : Bitfield<5, 3> {};
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struct Id_bits : Bitfield<19, 5> {};
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Gicd_typer(unsigned cpus)
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: Mmio_register("GICD_TYPER", Mmio_register::RO, 0x4, 4,
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It_lines_number::bits(31) | Cpu_number::bits(cpus-1) | Id_bits::bits(9)) {}
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} _typer { _cpu_cnt };
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struct Gicd_iidr : Genode::Register<32>, Mmio_register
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{
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struct Implementer : Bitfield<0, 12> {};
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struct Revision : Bitfield<12, 4> {};
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struct Variant : Bitfield<16, 4> {};
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struct Product_id : Bitfield<24, 8> {};
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Gicd_iidr()
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: Mmio_register("GICD_IIDR", Mmio_register::RO, 0x8, 4, 0x123) {}
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} _iidr;
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struct Gicd_igroupr : Irq_reg
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{
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Gicd_igroupr()
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: Irq_reg("GICD_IGROUPR", Mmio_register::RW, 0x80, 1, 1024) {}
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} _igroupr;
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struct Gicd_isenabler : Irq_reg
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{
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Register read(Irq & irq) { return irq.enabled(); }
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void write(Irq & irq, Register v) { if (v) irq.enable(); }
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Gicd_isenabler()
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: Irq_reg("GICD_ISENABLER", Mmio_register::RW, 0x100, 1, 1024) {}
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} _isenabler;
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struct Gicd_icenabler : Irq_reg
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{
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Register read(Irq & irq) { return irq.enabled(); }
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void write(Irq & irq, Register v) { if (v) irq.disable(); }
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Gicd_icenabler()
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: Irq_reg("GICD_ICENABLER", Mmio_register::RW, 0x180, 1, 1024) {}
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} _csenabler;
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struct Gicd_ispendr : Irq_reg
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{
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Register read(Irq & irq) { return irq.pending(); }
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void write(Irq & irq, Register v) { if (v) irq.assert(); }
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Gicd_ispendr()
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: Irq_reg("GICD_ISPENDR", Mmio_register::RW, 0x200, 1, 1024) {}
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} _ispendr;
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struct Gicd_icpendr : Irq_reg
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{
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Register read(Irq & irq) { return irq.pending(); }
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void write(Irq & irq, Register v) { if (v) irq.deassert(); }
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Gicd_icpendr()
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: Irq_reg("GICD_ICPENDR", Mmio_register::RW, 0x280, 1, 1024) {}
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} _icpendr;
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struct Gicd_isactiver : Irq_reg
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{
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Register read(Irq & irq) { return irq.active(); }
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void write(Irq & irq, Register v) { if (v) irq.activate(); }
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Gicd_isactiver()
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: Irq_reg("GICD_ISACTIVER", Mmio_register::RW, 0x300, 1, 1024) {}
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} _isactiver;
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struct Gicd_icactiver : Irq_reg
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{
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Register read(Irq & irq) { return irq.active(); }
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void write(Irq & irq, Register v) { if (v) irq.deactivate(); }
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Gicd_icactiver()
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: Irq_reg("GICD_ICACTIVER", Mmio_register::RW, 0x380, 1, 1024) {}
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} _icactiver;
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struct Gicd_ipriorityr : Irq_reg
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{
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Register read(Irq & irq) { return irq.priority(); }
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void write(Irq & irq, Register v) { irq.priority(v); }
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Gicd_ipriorityr()
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: Irq_reg("GICD_IPRIORITYR", Mmio_register::RW, 0x400, 8, 1024) {}
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} _ipriorityr;
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struct Gicd_itargetr : Irq_reg
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{
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Register read(Irq & irq) { return irq.target(); }
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void write(Irq & irq, Register v) { irq.target(v); }
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Gicd_itargetr()
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: Irq_reg("GICD_ITARGETSR", Mmio_register::RW, 0x800, 8, 1024) {}
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} _itargetr;
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struct Gicd_icfgr : Irq_reg
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{
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Register read(Irq & irq) { return irq.level() ? 0 : 1; }
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void write(Irq & irq, Register v) { irq.level(!v); }
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Gicd_icfgr()
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: Irq_reg("GICD_ICFGR", Mmio_register::RW, 0xc00, 8, 1024) {}
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} _icfgr;
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struct Gicd_sgir : Genode::Register<32>, Mmio_register
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{
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struct Enable : Bitfield<0, 1> {};
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struct Disable : Bitfield<6, 1> {};
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void write(Address_range & access, Cpu & cpu,
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Mmio_register::Register value) override
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{
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Genode::error("SGIR WRITE ", value);
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}
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Gicd_sgir()
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: Mmio_register("GICD_SGIR", Mmio_register::WO, 0xf00, 4, 0) {}
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} _sgir;
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struct Gicd_irouter : Irq_reg
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{
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Register read(Irq &) { return 0x0; } // FIXME smp
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void write(Irq &, Register) { }
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Gicd_irouter()
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: Irq_reg("GICD_IROUTER", Mmio_register::RW, 0x6100, 64, 1024) {}
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} _irouter;
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/**
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* FIXME: missing registers:
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* GICD_IGROUP = 0x80,
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* GICD_NSACR = 0xe00,
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* GICD_SGIR = 0xf00,
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* GICD_CPENDSGIR0 = 0xf10,
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* GICD_SPENDSGIR0 = 0xf20,
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* GICD identification registers 0xfd0...
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*/
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/**
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* Dummy container for holding array of noncopyable objects
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* Workaround for gcc bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70395
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*/
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struct Dummy {
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Mmio_register regs[8];
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} _reg_container { .regs = {
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{ "GICD_PIDR4", Mmio_register::RO, 0xffd0, 4, 0x0 },
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{ "GICD_PIDR5", Mmio_register::RO, 0xffd4, 4, 0x0 },
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{ "GICD_PIDR6", Mmio_register::RO, 0xffd8, 4, 0x0 },
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{ "GICD_PIDR7", Mmio_register::RO, 0xffdc, 4, 0x0 },
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{ "GICD_PIDR0", Mmio_register::RO, 0xffe0, 4, 0x492 },
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{ "GICD_PIDR1", Mmio_register::RO, 0xffe4, 4, 0xb0 },
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{ "GICD_PIDR2", Mmio_register::RO, 0xffe8, 4, (_version<<4) | 0xb },
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{ "GICD_PIDR3", Mmio_register::RO, 0xffec, 4, 0x44 }
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}};
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};
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#endif /* _SRC__SERVER__VMM__GIC_H_ */
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