94ea3a0acb
Driver definitions which are used by kernel/core in base-hw, and also by other drivers (e.g. from the os repository) have to reside in the generic base-repository, for instance some uart drivers. All drivers which are interesting for one of the sites only (sp804 for timer driver, or cortex_a9 cpu driver for base-hw) should reside in the respective repos. Factorize cpu context out of Cortex A9 specific definitions. Moreover, there is already a Cpu_state object containing all common ARM registers. We use this as a base for the cpu context switching done by the base-hw kernel. The Cpu_state class get extended by a cpu-exception field, that stores the kind of exception raised when the corresponding context got interrupted. This information is used not only by the base-hw kernel, but also by the TrustZone VMM that is build currently.
76 lines
1.8 KiB
C++
76 lines
1.8 KiB
C++
/*
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* \brief CPU state
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* \author Norman Feske
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* \author Stefan Kalkowski
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* \date 2011-05-06
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ARM__CPU__CPU_STATE_H_
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#define _INCLUDE__ARM__CPU__CPU_STATE_H_
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#include <base/stdint.h>
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namespace Genode {
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struct Cpu_state
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{
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/**
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* Native exception types
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*/
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enum Cpu_exception {
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RESET = 1,
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UNDEFINED_INSTRUCTION = 2,
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SUPERVISOR_CALL = 3,
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PREFETCH_ABORT = 4,
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DATA_ABORT = 5,
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INTERRUPT_REQUEST = 6,
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FAST_INTERRUPT_REQUEST = 7,
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MAX_CPU_EXCEPTION = FAST_INTERRUPT_REQUEST,
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};
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enum { MAX_GPR = 13 };
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addr_t r[MAX_GPR]; /* r0-r12 - general purpose */
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addr_t sp; /* r13 - stack pointer */
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addr_t lr; /* r14 - link register */
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addr_t ip; /* r15 - instruction pointer */
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addr_t cpsr; /* current program status register */
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Cpu_exception cpu_exception; /* last exception */
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};
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struct Cpu_state_modes : Cpu_state
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{
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/**
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* Common banked registers for exception modes
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*/
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struct Mode_state {
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enum Mode {
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UND, /* Undefined */
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SVC, /* Supervisor */
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ABORT, /* Abort */
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IRQ, /* Interrupt */
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FIQ, /* Fast Interrupt */
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MAX
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};
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uint32_t sp; /* banked stack pointer */
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uint32_t lr; /* banked link register */
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uint32_t spsr; /* saved program status register */
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};
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Mode_state mode[Mode_state::MAX]; /* exception mode registers */
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uint32_t fiq_r[5]; /* fast-interrupt mode r8-r12 */
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};
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}
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#endif /* _INCLUDE__ARM__CPU__CPU_STATE_H_ */
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