165 lines
4.8 KiB
C++
165 lines
4.8 KiB
C++
/*
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* \brief VMM cpu object
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* \author Stefan Kalkowski
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* \date 2019-07-18
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__SERVER__VMM__CPU_H_
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#define _SRC__SERVER__VMM__CPU_H_
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#include <cpu_base.h>
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namespace Vmm { class Cpu; }
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class Vmm::Cpu : public Vmm::Cpu_base
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{
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public:
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Cpu(Vm & vm,
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Genode::Vm_connection & vm_session,
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Mmio_bus & bus,
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Gic & gic,
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Genode::Env & env,
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Genode::Heap & heap,
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Genode::Entrypoint & ep);
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enum Exception_type {
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AARCH64_SYNC = 0x400,
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AARCH64_IRQ = 0x480,
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AARCH64_FIQ = 0x500,
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AARCH64_SERROR = 0x580,
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AARCH32_SYNC = 0x600,
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AARCH32_IRQ = 0x680,
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AARCH32_FIQ = 0x700,
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AARCH32_SERROR = 0x780,
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NO_EXCEPTION = 0xffff
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};
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private:
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class Id_aa64pfr0 : public System_register,
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public Genode::Register<64>
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{
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private:
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struct El0 : Bitfield<0, 4> { enum { AARCH64_ONLY = 1 }; };
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struct El1 : Bitfield<4, 4> { enum { AARCH64_ONLY = 1 }; };
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struct El2 : Bitfield<8, 4> { enum { NOT_IMPLEMENTED }; };
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struct El3 : Bitfield<12, 4> { enum { NOT_IMPLEMENTED }; };
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struct Ras : Bitfield<28, 4> { enum { NOT_IMPLEMENTED }; };
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struct Sve : Bitfield<32, 4> { enum { NOT_IMPLEMENTED }; };
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access_t _reset_value(access_t orig)
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{
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El0::set(orig, El0::AARCH64_ONLY);
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El1::set(orig, El1::AARCH64_ONLY);
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El2::set(orig, El2::NOT_IMPLEMENTED);
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El3::set(orig, El3::NOT_IMPLEMENTED);
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Ras::set(orig, Ras::NOT_IMPLEMENTED);
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Sve::set(orig, Sve::NOT_IMPLEMENTED);
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return orig;
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}
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public:
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Id_aa64pfr0(Genode::uint64_t id_aa64pfr0,
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Genode::Avl_tree<System_register> & tree)
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: System_register(3, 0, 0, 4, 0, "ID_AA64PFR0_EL1", false,
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_reset_value(id_aa64pfr0), tree) {}
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};
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struct Ccsidr : System_register
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{
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System_register & csselr;
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State & state;
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Ccsidr(System_register &csselr,
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State & state,
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Genode::Avl_tree<System_register> & tree)
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: System_register(3, 0, 1, 0, 0, "CCSIDR_EL1", false, 0x0, tree),
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csselr(csselr), state(state) {}
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virtual Genode::addr_t read() const override;
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};
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struct Ctr_el0 : System_register
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{
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Ctr_el0(Genode::Avl_tree<System_register> & tree)
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: System_register(3, 0, 3, 0, 1, "CTR_EL0", false, 0x0, tree) {}
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virtual Genode::addr_t read() const override;
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};
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struct Icc_sgi1r_el1 : System_register
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{
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Vm & vm;
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Icc_sgi1r_el1(Genode::Avl_tree<System_register> & tree, Vm & vm)
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: System_register(3, 12, 0, 11, 5, "SGI1R_EL1", true, 0x0, tree),
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vm(vm) {}
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virtual void write(Genode::addr_t v) override;
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};
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/******************************
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** Identification registers **
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******************************/
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System_register _sr_id_aa64afr0_el1;
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System_register _sr_id_aa64afr1_el1;
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System_register _sr_id_aa64dfr0_el1;
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System_register _sr_id_aa64dfr1_el1;
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System_register _sr_id_aa64isar0_el1;
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System_register _sr_id_aa64isar1_el1;
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System_register _sr_id_aa64mmfr0_el1;
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System_register _sr_id_aa64mmfr1_el1;
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System_register _sr_id_aa64mmfr2_el1;
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Id_aa64pfr0 _sr_id_aa64pfr0_el1;
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System_register _sr_id_aa64pfr1_el1;
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System_register _sr_id_aa64zfr0_el1;
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System_register _sr_aidr_el1;
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System_register _sr_revidr_el1;
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/*********************
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** Cache registers **
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*********************/
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System_register _sr_clidr_el1;
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System_register _sr_csselr_el1;
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Ctr_el0 _sr_ctr_el0;
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Ccsidr _sr_ccsidr_el1;
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/***********************************
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** Performance monitor registers **
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***********************************/
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System_register _sr_pmuserenr_el0;
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/*****************************
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** Debug monitor registers **
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*****************************/
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System_register _sr_dbgbcr0;
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System_register _sr_dbgbvr0;
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System_register _sr_dbgwcr0;
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System_register _sr_dbgwvr0;
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System_register _sr_mdscr;
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System_register _sr_osdlr;
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System_register _sr_oslar;
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/***********************
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** GIC cpu interface **
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***********************/
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Icc_sgi1r_el1 _sr_sgi1r_el1;
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};
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#endif /* _SRC__SERVER__VMM__CPU_H_ */
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