248 lines
7.4 KiB
C++
248 lines
7.4 KiB
C++
/*
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* \brief VMM cpu object
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* \author Stefan Kalkowski
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* \date 2019-07-18
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <cpu.h>
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#include <vm.h>
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#include <psci.h>
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using Vmm::Cpu_base;
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using Vmm::Cpu;
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using Vmm::Gic;
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Genode::uint64_t Cpu_base::State::reg(unsigned idx) const
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{
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if (idx > 30) return 0;
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return r[idx];
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}
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void Cpu_base::State::reg(unsigned idx, Genode::uint64_t v)
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{
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if (idx > 30) return;
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r[idx] = v;
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}
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Cpu_base::System_register::Iss::access_t
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Cpu_base::System_register::Iss::value(unsigned op0, unsigned crn, unsigned op1,
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unsigned crm, unsigned op2)
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{
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access_t v = 0;
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Crn::set(v, crn);
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Crm::set(v, crm);
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Opcode0::set(v, op0);
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Opcode1::set(v, op1);
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Opcode2::set(v, op2);
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return v;
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};
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Cpu_base::System_register::Iss::access_t
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Cpu_base::System_register::Iss::mask_encoding(access_t v)
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{
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return Crm::masked(v) |
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Crn::masked(v) |
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Opcode1::masked(v) |
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Opcode2::masked(v) |
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Opcode0::masked(v);
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}
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void Cpu_base::_handle_brk()
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{
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Genode::uint64_t offset = 0x0;
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if (!(_state.pstate & 0b100)) {
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offset = 0x400;
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} else if (_state.pstate & 0b1) {
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offset = 0x200;
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}
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_state.esr_el1 = _state.esr_el2;
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_state.spsr_el1 = _state.pstate;
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_state.elr_el1 = _state.ip;
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_state.ip = _state.vbar_el1 + offset;
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_state.pstate = 0b1111000101;
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}
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void Cpu_base::handle_exception()
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{
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/* check exception reason */
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switch (_state.exception_type) {
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case Cpu::NO_EXCEPTION: break;
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case Cpu::AARCH64_IRQ: _handle_irq(); break;
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case Cpu::AARCH64_SYNC: _handle_sync(); break;
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default:
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throw Exception("Curious exception ",
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_state.exception_type, " occured");
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}
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_state.exception_type = Cpu::NO_EXCEPTION;
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}
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void Cpu_base::dump()
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{
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using namespace Genode;
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auto lambda = [] (addr_t exc) {
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switch (exc) {
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case Cpu::AARCH64_SYNC: return "aarch64 sync";
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case Cpu::AARCH64_IRQ: return "aarch64 irq";
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case Cpu::AARCH64_FIQ: return "aarch64 fiq";
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case Cpu::AARCH64_SERROR: return "aarch64 serr";
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case Cpu::AARCH32_SYNC: return "aarch32 sync";
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case Cpu::AARCH32_IRQ: return "aarch32 irq";
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case Cpu::AARCH32_FIQ: return "aarch32 fiq";
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case Cpu::AARCH32_SERROR: return "aarch32 serr";
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default: return "unknown";
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};
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};
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log("VM state (", _active ? "active" : "inactive", ") :");
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for (unsigned i = 0; i < 31; i++) {
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log(" r", i, " = ",
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Hex(_state.r[i], Hex::PREFIX, Hex::PAD));
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}
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log(" sp = ", Hex(_state.sp, Hex::PREFIX, Hex::PAD));
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log(" ip = ", Hex(_state.ip, Hex::PREFIX, Hex::PAD));
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log(" sp_el1 = ", Hex(_state.sp_el1, Hex::PREFIX, Hex::PAD));
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log(" elr_el1 = ", Hex(_state.elr_el1, Hex::PREFIX, Hex::PAD));
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log(" pstate = ", Hex(_state.pstate, Hex::PREFIX, Hex::PAD));
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log(" exception = ", _state.exception_type, " (",
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lambda(_state.exception_type), ")");
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log(" esr_el2 = ", Hex(_state.esr_el2, Hex::PREFIX, Hex::PAD));
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_timer.dump();
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}
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Genode::addr_t Cpu::Ccsidr::read() const
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{
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struct Clidr : Genode::Register<32>
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{
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enum Cache_entry {
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NO_CACHE,
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INSTRUCTION_CACHE_ONLY,
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DATA_CACHE_ONLY,
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SEPARATE_CACHE,
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UNIFIED_CACHE
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};
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static unsigned level(unsigned l, access_t reg) {
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return (reg >> l*3) & 0b111; }
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};
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struct Csselr : Genode::Register<32>
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{
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struct Instr : Bitfield<0, 1> {};
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struct Level : Bitfield<1, 4> {};
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};
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enum { INVALID = 0xffffffff };
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unsigned level = Csselr::Level::get(csselr.read());
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bool instr = Csselr::Instr::get(csselr.read());
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if (level > 6) {
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Genode::warning("Invalid Csselr value!");
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return INVALID;
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}
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unsigned ce = Clidr::level(level, state.clidr_el1);
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if (ce == Clidr::NO_CACHE ||
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(ce == Clidr::DATA_CACHE_ONLY && instr)) {
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Genode::warning("Invalid Csselr value!");
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return INVALID;
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}
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if (ce == Clidr::INSTRUCTION_CACHE_ONLY ||
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(ce == Clidr::SEPARATE_CACHE && instr)) {
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Genode::log("Return Ccsidr instr value ", state.ccsidr_inst_el1[level]);
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return state.ccsidr_inst_el1[level];
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}
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Genode::log("Return Ccsidr value ", state.ccsidr_data_el1[level]);
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return state.ccsidr_data_el1[level];
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}
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Genode::addr_t Cpu::Ctr_el0::read() const
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{
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Genode::addr_t ret;
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asm volatile("mrs %0, ctr_el0" : "=r" (ret));
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return ret;
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}
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void Cpu::Icc_sgi1r_el1::write(Genode::addr_t v)
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{
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unsigned target_list = v & 0xffff;
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unsigned irq = (v >> 24) & 0xf;
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for (unsigned i = 0; i <= Vm::last_cpu(); i++) {
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if (target_list & (1<<i)) {
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vm.cpu(i, [&] (Cpu & cpu) {
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cpu.gic().irq(irq).assert();
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cpu.recall();
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});
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}
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}
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};
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void Cpu_base::initialize_boot(Genode::addr_t ip, Genode::addr_t dtb)
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{
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state().reg(0, dtb);
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state().ip = ip;
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}
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Cpu::Cpu(Vm & vm,
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Genode::Vm_connection & vm_session,
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Mmio_bus & bus,
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Gic & gic,
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Genode::Env & env,
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Genode::Heap & heap,
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Genode::Entrypoint & ep)
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: Cpu_base(vm, vm_session, bus, gic, env, heap, ep),
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_sr_id_aa64afr0_el1 (3, 0, 0, 5, 4, "ID_AA64AFR0_EL1", false, 0x0, _reg_tree),
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_sr_id_aa64afr1_el1 (3, 0, 0, 5, 5, "ID_AA64AFR1_EL1", false, 0x0, _reg_tree),
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_sr_id_aa64dfr0_el1 (3, 0, 0, 5, 0, "ID_AA64DFR0_EL1", false, 0x6, _reg_tree),
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_sr_id_aa64dfr1_el1 (3, 0, 0, 5, 1, "ID_AA64DFR1_EL1", false, 0x0, _reg_tree),
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_sr_id_aa64isar0_el1(3, 0, 0, 6, 0, "ID_AA64ISAR0_EL1", false, _state.id_aa64isar0_el1, _reg_tree),
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_sr_id_aa64isar1_el1(3, 0, 0, 6, 1, "ID_AA64ISAR1_EL1", false, _state.id_aa64isar1_el1, _reg_tree),
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_sr_id_aa64mmfr0_el1(3, 0, 0, 7, 0, "ID_AA64MMFR0_EL1", false, _state.id_aa64mmfr0_el1, _reg_tree),
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_sr_id_aa64mmfr1_el1(3, 0, 0, 7, 1, "ID_AA64MMFR1_EL1", false, _state.id_aa64mmfr1_el1, _reg_tree),
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_sr_id_aa64mmfr2_el1(3, 0, 0, 7, 2, "ID_AA64MMFR2_EL1", false, _state.id_aa64mmfr2_el1, _reg_tree),
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_sr_id_aa64pfr0_el1 (_state.id_aa64pfr0_el1, _reg_tree),
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_sr_id_aa64pfr1_el1 (3, 0, 0, 4, 1, "ID_AA64PFR1_EL1", false, 0x0, _reg_tree),
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_sr_id_aa64zfr0_el1 (3, 0, 0, 4, 4, "ID_AA64ZFR0_EL1", false, 0x0, _reg_tree),
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_sr_aidr_el1 (3, 0, 1, 0, 7, "AIDR_EL1", false, 0x0, _reg_tree),
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_sr_revidr_el1 (3, 0, 0, 0, 6, "REVIDR_EL1", false, 0x0, _reg_tree),
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_sr_clidr_el1 (3, 0, 1, 0, 1, "CLIDR_EL1", false, _state.clidr_el1, _reg_tree),
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_sr_csselr_el1 (3, 0, 2, 0, 0, "CSSELR_EL1", true, 0x0, _reg_tree),
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_sr_ctr_el0 (_reg_tree),
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_sr_ccsidr_el1 (_sr_csselr_el1, _state, _reg_tree),
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_sr_pmuserenr_el0 (3, 9, 3, 14, 0, "PMUSEREN_EL0", true, 0x0, _reg_tree),
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_sr_dbgbcr0 (2, 0, 0, 0, 5, "DBGBCR_EL1", true, 0x0, _reg_tree),
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_sr_dbgbvr0 (2, 0, 0, 0, 4, "DBGBVR_EL1", true, 0x0, _reg_tree),
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_sr_dbgwcr0 (2, 0, 0, 0, 7, "DBGWCR_EL1", true, 0x0, _reg_tree),
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_sr_dbgwvr0 (2, 0, 0, 0, 6, "DBGWVR_EL1", true, 0x0, _reg_tree),
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_sr_mdscr (2, 0, 0, 2, 2, "MDSCR_EL1", true, 0x0, _reg_tree),
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_sr_osdlr (2, 1, 0, 3, 4, "OSDLR_EL1", true, 0x0, _reg_tree),
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_sr_oslar (2, 1, 0, 0, 4, "OSLAR_EL1", true, 0x0, _reg_tree),
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_sr_sgi1r_el1 (_reg_tree, vm)
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{
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_state.pstate = 0b1111000101; /* el1 mode and IRQs disabled */
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_state.vmpidr_el2 = cpu_id();
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}
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