216 lines
7.5 KiB
ArmAsm
216 lines
7.5 KiB
ArmAsm
/*
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* \brief Transition between virtual/host mode
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* \author Stefan Kalkowski
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* \date 2015-02-16
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.set USR_MODE, 16
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.set FIQ_MODE, 17
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.set IRQ_MODE, 18
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.set SVC_MODE, 19
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.set ABT_MODE, 23
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.set UND_MODE, 27
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.set SYS_MODE, 31
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.macro _save_bank mode
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cps #\mode /* switch to given mode */
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mrs r1, spsr /* store mode-specific spsr */
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stmia r0!, {r1,sp,lr} /* store mode-specific sp and lr */
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.endm /* _save_bank mode */
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.macro _restore_bank mode
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cps #\mode /* switch to given mode */
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ldmia r0!, {r1,sp,lr} /* load mode-specific sp, lr, and spsr into r1 */
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msr spsr_cxfs, r1 /* load mode-specific spsr */
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.endm
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.macro _vm_exit exception_type
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str r0, [sp]
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mrc p15, 4, r0, c1, c1, 0 /* read HCR register */
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tst r0, #1 /* check VM bit */
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ldreq r0, [sp]
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beq _host_to_vm
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mov r0, #\exception_type
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str r0, [sp, #17*4]
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b _vm_to_host
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.endm /* _vm_exit */
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.section .text
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/*
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* On virtualization exceptions the CPU has to jump to one of the following
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* 7 entry vectors to switch to a kernel context.
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*/
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.p2align 12
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.global hypervisor_exception_vector
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hypervisor_exception_vector:
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b _vt_rst_entry
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b _vt_und_entry /* undefined instruction */
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b _vt_svc_entry /* hypervisor call */
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b _vt_pab_entry /* prefetch abort */
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b _vt_dab_entry /* data abort */
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b _vt_trp_entry /* hypervisor trap */
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b _vt_irq_entry /* interrupt request */
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_vm_exit 7 /* fast interrupt request */
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_vt_rst_entry: _vm_exit 1
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_vt_und_entry: _vm_exit 2
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_vt_svc_entry: _vm_exit 3
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_vt_pab_entry: _vm_exit 4
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_vt_dab_entry: _vm_exit 5
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_vt_irq_entry: _vm_exit 6
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_vt_trp_entry: _vm_exit 8
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_host_to_vm:
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msr elr_hyp, r2
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msr spsr_cxfs, r3 /* load cpsr */
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mcrr p15, 6, r5, r6, c2 /* write VTTBR */
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mcr p15, 0, r7, c1, c0, 0 /* write SCTRL */
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mcr p15, 4, r8, c1, c1, 3 /* write HSTR */
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mcr p15, 4, r9, c1, c1, 0 /* write HCR register */
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mcr p15, 0, r12, c2, c0, 2 /* write TTBRC */
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sub sp, r0, #46*4
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ldm r0!, {r1-r12}
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mcr p15, 0, r1, c2, c0, 0 /* write TTBR0 */
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mcr p15, 0, r2, c2, c0, 1 /* write TTBR1 */
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mcr p15, 0, r3, c10, c2, 0 /* write PRRR */
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mcr p15, 0, r4, c10, c2, 1 /* write NMRR */
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mcr p15, 0, r5, c3, c0, 0 /* write DACR */
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mcr p15, 0, r6, c5, c0, 0 /* write DFSR */
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mcr p15, 0, r7, c5, c0, 1 /* write IFSR */
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mcr p15, 0, r8, c5, c1, 0 /* write ADFSR */
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mcr p15, 0, r9, c5, c1, 1 /* write AIFSR */
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mcr p15, 0, r10, c6, c0, 0 /* write DFAR */
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mcr p15, 0, r11, c6, c0, 2 /* write IFAR */
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mcr p15, 0, r12, c13, c0, 1 /* write CIDR */
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ldm r0!, {r1-r4}
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mcr p15, 0, r1, c13, c0, 2 /* write TLS1 */
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mcr p15, 0, r2, c13, c0, 3 /* write TLS2 */
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mcr p15, 0, r3, c13, c0, 4 /* write TLS3 */
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mcr p15, 0, r4, c1, c0, 2 /* write CPACR */
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ldr r1, [r0]
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vmsr fpscr, r1
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add r1, r0, #4
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vldm r1!, {d0-d15}
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vldm r1!, {d16-d31}
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ldm r1!, {r2-r7}
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mcrr p15, 4, r2, r3, c14 /* write cntvoff */
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mcrr p15, 3, r4, r5, c14 /* write cntv_cval */
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mcr p15, 0, r6, c14, c3, 1 /* write cntv_ctl */
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mcr p15, 0, r7, c14, c1, 0 /* write cntkctl */
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ldmia sp, {r0-r12} /* load vm's r0-r12 */
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eret
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_vm_to_host:
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add r0, sp, #1*4
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stmia r0, {r1-r12} /* save regs r1-r12 */
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mov r1, #0
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mcrr p15, 6, r1, r1, c2 /* write VTTBR */
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mcr p15, 4, r1, c1, c1, 0 /* write HCR register */
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mcr p15, 4, r1, c1, c1, 3 /* write HSTR register */
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mrs r1, ELR_hyp /* read ip */
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mrs r2, spsr /* read cpsr */
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mrc p15, 0, r3, c1, c0, 0 /* read SCTRL */
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mrc p15, 4, r4, c5, c2, 0 /* read HSR */
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mrc p15, 4, r5, c6, c0, 4 /* read HPFAR */
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mrc p15, 4, r6, c6, c0, 0 /* read HDFAR */
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mrc p15, 4, r7, c6, c0, 2 /* read HIFAR */
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mrc p15, 0, r8, c2, c0, 2 /* read TTBRC */
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mrc p15, 0, r9, c2, c0, 0 /* read TTBR0 */
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mrc p15, 0, r10, c2, c0, 1 /* read TTBR1 */
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mrc p15, 0, r11, c10, c2, 0 /* read PRRR */
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mrc p15, 0, r12, c10, c2, 1 /* read NMRR */
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add r0, sp, #40*4 /* offset SCTRL */
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stm r0!, {r3-r12}
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mrc p15, 0, r3, c3, c0, 0 /* read DACR */
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mrc p15, 0, r4, c5, c0, 0 /* read DFSR */
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mrc p15, 0, r5, c5, c0, 1 /* read IFSR */
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mrc p15, 0, r6, c5, c1, 0 /* read ADFSR */
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mrc p15, 0, r7, c5, c1, 1 /* read AIFSR */
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mrc p15, 0, r8, c6, c0, 0 /* read DFAR */
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mrc p15, 0, r9, c6, c0, 2 /* read IFAR */
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mrc p15, 0, r10, c13, c0, 1 /* read CIDR */
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mrc p15, 0, r11, c13, c0, 2 /* read TLS1 */
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mrc p15, 0, r12, c13, c0, 3 /* read TLS2 */
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stm r0!, {r3-r12}
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mrc p15, 0, r3, c13, c0, 4 /* read TLS3 */
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mrc p15, 0, r4, c1, c0, 2 /* read CPACR */
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stm r0!, {r3, r4}
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mov r3, #0xf
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lsl r3, #20
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mcr p15, 0, r3, c1, c0, 2 /* write CPACR */
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mov r3, #1 /* clear fpu exception state */
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lsl r3, #30
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vmsr fpexc, r3
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vmrs r4, fpscr
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stmia r0!, {r4}
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vstm r0!, {d0-d15}
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vstm r0!, {d16-d31}
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mrrc p15, 4, r3, r4, c14 /* read cntvoff */
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mrrc p15, 3, r5, r6, c14 /* read cntv_cval */
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mrc p15, 0, r7, c14, c3, 1 /* write cntv_ctl */
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mrc p15, 0, r8, c14, c1, 0 /* write cntkctl */
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stm r0!, {r3-r8}
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add r0, sp, #13*4
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ldr r3, _vt_host_context_ptr
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ldr sp, [r3]
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add r3, r3, #2*4
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ldm r3, {r4-r11}
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mcrr p15, 0, r6, r7, c2
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mcrr p15, 1, r6, r7, c2
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mcr p15, 0, r8, c1, c0, 0 /* write SCTRL */
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mcr p15, 0, r9, c2, c0, 2 /* write TTBRC */
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mcr p15, 0, r10, c10, c2, 0 /* write MAIR0 */
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mcr p15, 0, r11, c3, c0, 0 /* write DACR */
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mov r10, #7
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lsl r10, #6
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add r10, r10, #SVC_MODE
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msr spsr_cxsf, r10
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adr r10, _svc_mode_ret
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msr ELR_hyp, r10
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eret
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_svc_mode_ret:
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stmia r0, {r13-r14}^ /* save user regs sp,lr */
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add r0, r0, #2*4
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stmia r0!, {r1-r2} /* save ip, cpsr */
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add r0, r0, #1*4
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_save_bank UND_MODE /* save undefined banks */
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_save_bank SVC_MODE /* save supervisor banks */
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_save_bank ABT_MODE /* save abort banks */
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_save_bank IRQ_MODE /* save irq banks */
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_save_bank FIQ_MODE /* save fiq banks */
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stmia r0!, {r8-r12} /* save fiq r8-r12 */
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cps #SVC_MODE
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ldr r0, _vt_host_context_ptr
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ldm r0, {sp,pc}
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/* host kernel must jump to this point to switch to a vm */
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.global hypervisor_enter_vm
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hypervisor_enter_vm:
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add r0, r0, #13*4
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ldm r0, {r13 - r14}^
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add r0, r0, #2*4
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ldmia r0!, {r2 - r4}
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_restore_bank UND_MODE
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_restore_bank SVC_MODE
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_restore_bank ABT_MODE
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_restore_bank IRQ_MODE
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_restore_bank FIQ_MODE
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ldmia r0!, {r8 - r12}
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cps #SVC_MODE
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ldm r0!, {r5 - r12}
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hvc #0
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_vt_host_context_ptr: .long vt_host_context
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