116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* \brief Parts of platform that are specific to ARM virtualization
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2020-04-02
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*/
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/*
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* Copyright (C) 2020 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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static inline void prepare_nonsecure_world(unsigned long timer_freq)
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{
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using Cpu = Hw::Arm_cpu;
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/* if we are already in HYP mode we're done (depends on u-boot version) */
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if (Cpu::Psr::M::get(Cpu::Cpsr::read()) == Cpu::Psr::M::HYP)
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return;
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/* ARM generic timer counter freq needs to be set in secure mode */
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Cpu::Cntfrq::write(timer_freq);
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/*
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* enable coprocessor 10 + 11 access and SMP bit access in auxiliary control
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* register for non-secure world
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*/
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Cpu::Nsacr::access_t nsacr = 0;
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Cpu::Nsacr::Cpnsae10::set(nsacr, 1);
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Cpu::Nsacr::Cpnsae11::set(nsacr, 1);
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Cpu::Nsacr::Ns_smp::set(nsacr, 1);
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Cpu::Nsacr::write(nsacr);
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asm volatile (
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"msr sp_mon, sp \n" /* copy current mode's sp */
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"msr lr_mon, lr \n" /* copy current mode's lr */
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"cps #22 \n" /* switch to monitor mode */
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);
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Cpu::Scr::access_t scr = 0;
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Cpu::Scr::Ns::set(scr, 1);
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Cpu::Scr::Fw::set(scr, 1);
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Cpu::Scr::Aw::set(scr, 1);
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Cpu::Scr::Scd::set(scr, 1);
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Cpu::Scr::Hce::set(scr, 1);
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Cpu::Scr::Sif::set(scr, 1);
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Cpu::Scr::write(scr);
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}
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static inline void prepare_hypervisor(Genode::addr_t table)
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{
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using Cpu = Hw::Arm_cpu;
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/* set hypervisor exception vector */
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Cpu::Hvbar::write(Hw::Mm::hypervisor_exception_vector().base);
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/* set hypervisor's translation table */
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Cpu::Httbr_64bit::write(table);
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Cpu::Ttbcr::access_t ttbcr = 0;
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Cpu::Ttbcr::Irgn0::set(ttbcr, 1);
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Cpu::Ttbcr::Orgn0::set(ttbcr, 1);
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Cpu::Ttbcr::Sh0::set(ttbcr, 2);
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Cpu::Ttbcr::Eae::set(ttbcr, 1);
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/* prepare MMU usage by hypervisor code */
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Cpu::Htcr::write(ttbcr);
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/* don't trap on cporocessor 10 + 11, but all others */
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Cpu::Hcptr::access_t hcptr = 0;
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Cpu::Hcptr::Tcp<0>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<1>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<2>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<3>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<4>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<5>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<6>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<7>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<8>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<9>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<12>::set(hcptr, 1);
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Cpu::Hcptr::Tcp<13>::set(hcptr, 1);
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Cpu::Hcptr::Tta::set(hcptr, 1);
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Cpu::Hcptr::write(hcptr);
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enum Memory_attributes {
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DEVICE_MEMORY = 0x04,
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NORMAL_MEMORY_UNCACHED = 0x44,
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NORMAL_MEMORY_CACHED = 0xff,
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};
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Cpu::Mair0::access_t mair0 = 0;
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Cpu::Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED);
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Cpu::Mair0::Attr1::set(mair0, DEVICE_MEMORY);
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Cpu::Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED);
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Cpu::Mair0::Attr3::set(mair0, DEVICE_MEMORY);
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Cpu::Hmair0::write(mair0);
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Cpu::Vtcr::access_t vtcr = ttbcr;
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Cpu::Vtcr::Sl0::set(vtcr, 1); /* set to starting level 1 */
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Cpu::Vtcr::write(vtcr);
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Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
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Cpu::Sctlr::C::set(sctlr, 1);
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Cpu::Sctlr::I::set(sctlr, 1);
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Cpu::Sctlr::V::set(sctlr, 1);
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Cpu::Sctlr::M::set(sctlr, 1);
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Cpu::Sctlr::Z::set(sctlr, 1);
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Cpu::Hsctlr::write(sctlr);
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}
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