90 lines
3.5 KiB
C++
90 lines
3.5 KiB
C++
/*
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* \brief x86_64 CPU definitions
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* \author Stefan Kalkowski
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* \date 2017-04-07
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__X86_64__CPU_H_
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#define _SRC__LIB__HW__SPEC__X86_64__CPU_H_
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#include <hw/spec/x86_64/register_macros.h>
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namespace Hw { struct X86_64_cpu; }
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struct Hw::X86_64_cpu
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{
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X86_64_CR_REGISTER(Cr0, cr0,
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struct Pe : Bitfield< 0, 1> { }; /* Protection Enable */
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struct Mp : Bitfield< 1, 1> { }; /* Monitor Coprocessor */
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struct Em : Bitfield< 2, 1> { }; /* Emulation */
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struct Ts : Bitfield< 3, 1> { }; /* Task Switched */
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struct Et : Bitfield< 4, 1> { }; /* Extension Type */
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struct Ne : Bitfield< 5, 1> { }; /* Numeric Error */
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struct Wp : Bitfield<16, 1> { }; /* Write Protect */
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struct Am : Bitfield<18, 1> { }; /* Alignment Mask */
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struct Nw : Bitfield<29, 1> { }; /* Not Write-through */
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struct Cd : Bitfield<30, 1> { }; /* Cache Disable */
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struct Pg : Bitfield<31, 1> { }; /* Paging */
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);
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/**
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* Control register 2: Page-fault linear address
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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X86_64_CR_REGISTER(Cr2, cr2,
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struct Addr : Bitfield<0, 63> { };
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);
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/**
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* Control register 3: Page-Directory base register
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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X86_64_CR_REGISTER(Cr3, cr3,
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struct Pwt : Bitfield<3,1> { }; /* Page-level write-through */
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struct Pcd : Bitfield<4,1> { }; /* Page-level cache disable */
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struct Pdb : Bitfield<12, 36> { }; /* Page-directory base address */
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);
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X86_64_CR_REGISTER(Cr4, cr4,
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struct Vme : Bitfield< 0, 1> { }; /* Virtual-8086 Mode Extensions */
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struct Pvi : Bitfield< 1, 1> { }; /* Protected-Mode Virtual IRQs */
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struct Tsd : Bitfield< 2, 1> { }; /* Time Stamp Disable */
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struct De : Bitfield< 3, 1> { }; /* Debugging Exceptions */
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struct Pse : Bitfield< 4, 1> { }; /* Page Size Extensions */
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struct Pae : Bitfield< 5, 1> { }; /* Physical Address Extension */
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struct Mce : Bitfield< 6, 1> { }; /* Machine-Check Enable */
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struct Pge : Bitfield< 7, 1> { }; /* Page Global Enable */
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struct Pce : Bitfield< 8, 1> { }; /* Performance-Monitoring Counter
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Enable*/
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struct Osfxsr : Bitfield< 9, 1> { }; /* OS Support for FXSAVE and
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FXRSTOR instructions*/
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struct Osxmmexcpt : Bitfield<10, 1> { }; /* OS Support for Unmasked
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SIMD/FPU Exceptions */
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struct Vmxe : Bitfield<13, 1> { }; /* VMX Enable */
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struct Smxe : Bitfield<14, 1> { }; /* SMX Enable */
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struct Fsgsbase : Bitfield<16, 1> { }; /* FSGSBASE-Enable */
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struct Pcide : Bitfield<17, 1> { }; /* PCIDE Enable */
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struct Osxsave : Bitfield<18, 1> { }; /* XSAVE and Processor Extended
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States-Enable */
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struct Smep : Bitfield<20, 1> { }; /* SMEP Enable */
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struct Smap : Bitfield<21, 1> { }; /* SMAP Enable */
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);
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X86_64_MSR_REGISTER(IA32_apic_base, 0x1b,
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struct Bsp : Bitfield< 8, 1> { }; /* Bootstrap processor */
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struct Lapic : Bitfield< 11, 1> { }; /* Enable/disable local APIC */
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struct Base : Bitfield< 12, 24> { }; /* Base address of APIC registers */
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);
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};
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#endif /* _SRC__LIB__HW__SPEC__X86_64__CPU_H_ */
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